Versal NOC

Versal NOC

 

 

 

 

 

 

 

The NoC was designed for scalability. It is composed of a series of interconnected horizontal(HNoC) and vertical (VNoC) paths.

The HNoC and VNoC are dedicated, high-bandwidth paths connecting integrated blocks between the processor system and the programmable logic (PL) without consuming large amounts of programmable logic.

 

 

The NoC components comprise NoC master units (NMU), NoC slave units (NSU).

 

The bottom HNoC typically connects to a selection of blocks such as PS, Platform Management Controller (PMC), Integrated block for PCIe with DMA and cache

coherent interconnect (CPM). and DDRMC (Integrated DDR Memory Controller) to list a few.

 

 

 

NoC Packet Switch (NPS): Used to perform transport and packet switching along the NoC and to set up and use virtual channels.

 

The DDR memory controller interface contains four dedicated NSU controllers. The DDR controllers are configured using the NoC IP Wizard.

 

NoC Inter-Die Bridge (NIDB): The block that bridges Vertical NoC (VNoC) between multiple Stacked Silicon Interconnect Technology (SSIT) dies.

 

• Fixed Burst Length 8 for DDR4.

• Fixed Burst Length 16 for LPDDR4.