简单幅值计算（复数的绝对值）---Verilog
1 //************************************************************************************************************** 2 //Function descriprion: Approximately replace the magnitude of a complex number with the absolute value sum of 3 //real part and imag part 4 5 //Input: clock,Real,Imag 6 //Output: absolute_value 7 //************************************************************************************************************** 8 9 `timescale 1ns/10ps 10 11 module Magnitude_Simplified_Computing( 12 13 input wire Clk, /*系统时钟******////// 14 input wire Rst_n, /*系统复位信号******////// 15 input wire DataEnable, 16 input wire [20:0] DataInRe, /*输入实部，位宽21位，二进制补码表示******////// 17 input wire [20:0] DataInIm, /*输入虚部******////// 18 output reg AbsoluteEnable, 19 output reg [21:0] Absolute); /*绝对值输出，经一次加法后，位宽变为22位，绝对值为正数******////// 20 21 //------------------------------------------------------------------------------- 22 23 reg BufferEnable; 24 reg [20:0] BufferDataRe; 25 reg [20:0] BufferDataIm; 26 27 always @ (posedge Clk or negedge Rst_n) /*输入增加一级缓存，延迟一个时钟周期******////// 28 begin 29 if (!Rst_n) 30 begin 31 BufferEnable <= 0; 32 BufferDataRe <= 0; 33 BufferDataIm <= 0; 34 end 35 else 36 begin /*缓存的数据为输入数据的绝对值******////// 37 if(DataEnable) 38 begin 39 BufferEnable <= 1; 40 if(DataInRe[20] == 0) /*符号位为0，表示为正数，绝对值即为输入数******////// 41 BufferDataRe <= DataInRe; 42 else /*符号位为1，表示为负数，绝对值为输入数取反加1******////// 43 BufferDataRe <= ~ DataInRe + 1; 44 45 if (DataInIm[20] == 0) /*虚部运算同实部******////// 46 BufferDataIm <= DataInIm; 47 else 48 BufferDataIm <= ~ DataInIm + 1; 49 end 50 else 51 begin 52 BufferEnable <= 0; 53 BufferDataRe <= 0; 54 BufferDataIm <= 0; 55 end 56 end 57 end 58 59 //------------------------------------------------------------------------------- 60 61 always @ (posedge Clk or negedge Rst_n) 62 begin 63 if (!Rst_n) 64 begin 65 Absolute <= 0; 66 AbsoluteEnable <= 0; 67 end 68 else 69 begin 70 if(BufferEnable) 71 begin 72 /*求取实部与虚部的绝对值之和******////// 73 Absolute <= {BufferDataRe[20],BufferDataRe} + {BufferDataIm[20],BufferDataIm}; 74 AbsoluteEnable <= 1; 75 end 76 else 77 begin 78 Absolute <= 0; 79 AbsoluteEnable <= 0; 80 end 81 end 82 end 83 84 endmodule
