数据量化---Verilog

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Posted on 2020-06-29 21:48 沉默改良者阅读(1151) 评论(0) 编辑收藏举报

数据量化---Verilog

  1 module Quantization(
  2 
  3 
  4     //moduel clock
  5     input                    wire                      Clk,
  6     //the reset signal
  7     input                    wire                      Rst_n,
  8     //the enable signal of the input datas
  9     input                    wire                      inEn,
 10     //the input datas: signed 1QN format
 11     input                    wire      [7:0]           bitInR,
 12     input                    wire      [7:0]           bitInI,
 13     //the enable signal of the Quantization results 
 14     output                   reg                       QuantizationEnable,
 15     //the quantization results
 16     output                   reg       [15:0]          Quantization_Result_Real,
 17     output                   reg       [15:0]          Quantization_Result_Imag);
 18 
 19 //-----------------------------------------------------------------------------------------
 20 
 21 //the enable signal buffer
 22 reg BufferEnable;
 23 //the input datas buffer
 24 reg [7:0]BufferDataR;
 25 reg [7:0]BufferDataI;
 26 
 27 always @(posedge Clk or negedge Rst_n)
 28 begin
 29     if(!Rst_n)
 30     begin
 31         BufferEnable <= 0;
 32         BufferDataR <= 0;
 33         BufferDataI <= 0;
 34     end
 35     else
 36     begin
 37         if(inEn)
 38         begin
 39             BufferEnable <= 1;
 40             BufferDataR <= bitInR;
 41             BufferDataI <= bitInI;
 42         end
 43         else
 44         begin
 45             BufferEnable <= 0;
 46             BufferDataR <= 0;
 47             BufferDataI <= 0;
 48         end
 49     end
 50 end
 51 
 52 //-----------------------------------------------------------------------------------------
 53 
 54 /*持续累加用寄存器 *//////
 55 reg [191:0] Continual_Accumulation_Real;          
 56 reg [191:0] Continual_Accumulation_Imag;
 57 /*持续累加有效信号 *//////
 58 reg AddEnable;    
 59 //********************************取得量化结果********************************//
 60 always @ (posedge Clk or negedge Rst_n)
 61 begin
 62        if (!Rst_n)
 63     begin
 64         Continual_Accumulation_Real <= 0;    
 65         Continual_Accumulation_Imag <= 0;
 66         AddEnable <= 0;
 67     end
 68     else
 69     begin
 70         if(BufferEnable)
 71         begin
 72             /*持续累加移位寄存器左移一个单元*****//////
 73             Continual_Accumulation_Real[191:12] <= Continual_Accumulation_Real[179:0];      
 74             Continual_Accumulation_Imag[191:12] <= Continual_Accumulation_Imag[179:0];
 75             /*最高一个单元与输入数据的12位扩展相加赋值给最低一个单元****//////
 76             Continual_Accumulation_Real[11:0] <= {{4{BufferDataR[7]}},BufferDataR} + Continual_Accumulation_Real[191:180]; 
 77             Continual_Accumulation_Imag[11:0] <= {{4{BufferDataI[7]}},BufferDataI} + Continual_Accumulation_Imag[191:180];
 78             AddEnable <= 1;
 79         end
 80         else
 81         begin
 82             Continual_Accumulation_Real <= 0;
 83             Continual_Accumulation_Imag <= 0;
 84             AddEnable <= 0;
 85         end
 86     end
 87 end
 88 
 89 //-----------------------------------------------------------------------------------------
 90 
 91 always @(posedge Clk or negedge Rst_n)
 92 begin
 93     if(!Rst_n)
 94     begin
 95         Quantization_Result_Real <= 0;
 96         Quantization_Result_Imag <= 0;    
 97         QuantizationEnable <= 0;
 98     end
 99     else
100     begin
101         if(AddEnable)
102         begin
103             QuantizationEnable <= 1;
104             /*量化结果移位******//////
105             Quantization_Result_Real[14:0] <= Quantization_Result_Real[15:1];            
106             Quantization_Result_Imag[14:0] <= Quantization_Result_Imag[15:1];
107             /*最高位为0，表正，量化为+1, 在此用0代替，下面语句只是用于判断******//////
108             Quantization_Result_Real[15] <= Continual_Accumulation_Real[11];
109             /*最高位为1，表负，量化为-1，在此用1表示******//////
110             Quantization_Result_Imag[15] <= Continual_Accumulation_Imag[11];     
111         end
112         else
113         begin
114             Quantization_Result_Real <= 0;
115             Quantization_Result_Imag <= 0;    
116             QuantizationEnable <= 0;
117         end
118     end
119 end
120 
121 endmodule