数据组合---Verilog

数据组合---Verilog

module Data_Combination(

    input          wire                  Clk,
    input          wire                  Rst_n,

    input          wire                  ShortTrainingEnable,
    input          wire    [7:0]         ShortTrainingRe,
    input          wire    [7:0]         ShortTrainingIm,

    input          wire                  otherFOEDataEnable,
    input          wire    [7:0]         otherFOEDataRe,
    input          wire    [7:0]         otherFOEDataIm,

    output         reg                   FOEDataOutEnable,
    output         reg     [7:0]         FOEDataOutRe,
    output         reg     [7:0]         FOEDataOutIm);


always@(posedge Clk or negedge Rst_n)
begin
    if (!Rst_n)
    begin
        FOEDataOutEnable <= 0;
        FOEDataOutRe <= 8'b00000000;
        FOEDataOutIm <= 8'b00000000;
    end
    else
    begin
        if (ShortTrainingEnable)
        begin
              /*延时后的短训练序列有效      ******///////
            FOEDataOutEnable <= 1;
            FOEDataOutRe <= ShortTrainingRe;
            FOEDataOutIm <= ShortTrainingIm;
        end
        else
        begin
              if (otherFOEDataEnable)
            begin
                   //长训练和数据序列校正后有效    ******////////             
                FOEDataOutEnable <= 1;
                FOEDataOutRe <= otherFOEDataRe;
                FOEDataOutIm <= otherFOEDataIm;
            end
            else
            begin
                FOEDataOutEnable <= 0;
                FOEDataOutRe <= 8'b00000000;
                FOEDataOutIm <= 8'b00000000;
            end
        end
    end
end


endmodule