查找一段信号的累加峰值---verilog
1 module Peak_Finding( 2 3 input wire Clk, 4 input wire Rst_n, 5 input wire DataEnable, 6 input wire [21:0] AbsoluteData; 7 output reg PeakFinded); 8 9 //---------------------------------------------------------------------- 10 //the enable singal buffer 11 reg BufferEnable; 12 //the input data buffer 13 reg [21:0]BufferData; 14 15 always @(posedge Clk or negedge Rst_n) 16 begin 17 if(!Rst_n) 18 begin 19 BufferEnable <= 0; 20 BufferData <= 0; 21 end 22 else 23 begin 24 if(DataEnable) 25 begin 26 BufferEnable <= 1; 27 BufferData <= AbsoluteData; 28 end 29 else 30 begin 31 BufferEnable <= 0; 32 BufferData <= 0; 33 end 34 end 35 end 36 37 //---------------------------------------------------------------------- 38 39 reg [3:0] STS_end_counter; /*峰值数目计数器******////// 40 41 always @(posedge Clk or negedge Rst_n) 42 begin 43 if(!Rst_n) 44 begin 45 STS_end_counter <= 0; 46 PeakFinded <= 0; 47 end 48 else 49 begin 50 if(BufferEnable) 51 begin /*absolute_sum位宽22位(1位符号位 + 7位整数位 + 14位小数位)******////// 52 if(STS_end_counter < 9) 53 begin 54 if (BufferData > 22'b0000_0001_10_0000_0000_0000) 55 STS_end_counter <= STS_end_counter + 1; /*大于阈值，计数器加1******////// 56 57 PeakFinded <= 0; 58 end 59 else 60 PeakFinded <= 1; /*当找到9个峰值，即短训练序列的结束位置，把信号拉高******////// 61 end 62 else 63 begin /*帧结束时，把寄存器赋予初始值******////// 64 STS_end_counter <= 0; 65 PeakFinded <= 0; 66 end 67 end 68 end 69 70 71 endmodule
