AXI总线slave模式下发送数据---verilog代码

AXI总线slave模式下发送数据---verilog代码

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: chensimin
// 
// Create Date: 2020/04/24 11:40:27
// Design Name: 
// Module Name: axi_slave_transmit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module axi_slave_transmit #
(
    parameter integer S_AXI_DATA_WIDTH    = 32,
    parameter integer S_AXI_ADDR_WIDTH    = 32
)
(
    input  wire                                s_axi_aclk,
    input  wire                                s_axi_aresetn,
    input  wire   [S_AXI_ADDR_WIDTH-1 : 0]     s_axi_araddr,
    input  wire                                s_axi_arvalid,
    output reg                                 s_axi_arready,
    output reg    [S_AXI_DATA_WIDTH-1 : 0]     s_axi_rdata = 0,
    output reg                                 s_axi_rvalid,
    input  wire                                s_axi_rready,
    output reg    [S_AXI_ADDR_WIDTH-1 : 0]     address,
    output reg                                 valid,
    input  wire   [S_AXI_DATA_WIDTH-1 : 0]     data
);

//---------------------------------------------------------------------------------

parameter  IDLE                = 0;
parameter  AREADY              = 1;
parameter  WAITING             = 2;
parameter  DATA                = 3;
parameter  READY               = 4;

//---------------------------------------------------------------------------------

reg [3:0] current_state = 0;
reg [3:0] next_state = 0;

always @(posedge s_axi_aclk or posedge s_axi_aresetn)
begin
    if(s_axi_aresetn == 1'b0)
        current_state <= IDLE;
    else
        current_state <= next_state;
end

//---------------------------------------------------------------------------------

always @(*)
begin
    case(current_state)
    IDLE:
    begin
        if(s_axi_arvalid)
            next_state <= AREADY;
        else 
            next_state <= IDLE;
    end
    AREADY:
    begin
        next_state <= WAITING;
    end
    WAITING:
    begin
        next_state <= DATA;
    end
    DATA:
    begin
        next_state <= READY;
    end
    READY:
    begin
        if(s_axi_rready)
            next_state <= IDLE;
        else 
            next_state <= READY;
    end
    default:
    begin
        next_state <= IDLE;
    end
    endcase
end

//---------------------------------------------------------------------------------

always @(posedge s_axi_aclk)
begin
    s_axi_arready  <= 1'b0;
    valid          <= 1'b0;
    address        <= 0;
    case(current_state)
    IDLE:
    begin
        s_axi_rvalid <= 1'b0;
    end
    AREADY:
    begin
        address <= s_axi_araddr;
        valid   <= 1'b1;
        s_axi_arready <= 1'b1;
    end
    DATA:
    begin
        s_axi_rdata  <= data;
        s_axi_rvalid <= 1'b1;
    end
    READY:
    begin
        if(s_axi_rready)
            s_axi_rvalid <= 1'b0;
    end
    default:
    begin
        s_axi_rvalid   <= 1'b0;
    end
    endcase
end

endmodule