am335x ti SDK6.0 kernel 时钟源码文件记录

• 源码流程记录

• 板级文件开始

    // arch/arm/mach-omap2/board-aplex_cmi_at101.c
    MACHINE_START(APLEX_CMI_AT101, "aplex_CMI_AT101")
        /* Maintainer: Texas Instruments */
        .atag_offset    = 0x100,
        .map_io     = am335x_evm_map_io,
        .init_early = am33xx_init_early,    --->   am33xx 前置初始化
        .init_irq   = ti81xx_init_irq,
       .handle_irq     = omap3_intc_handle_irq,
        .timer      = &omap3_am33xx_timer,
        .init_machine   = am335x_evm_init,
    MACHINE_END

• 整个 33xx 体系的前置初始化

    //  arch/arm/mach-omap2/io.c
    void __init am33xx_init_early(void)
    {
        omap2_set_globals_am33xx();
        omap3xxx_check_revision();
        am33xx_check_features();
        omap_common_init_early();
        am33xx_voltagedomains_init();
        omap44xx_prminst_init();
        am33xx_powerdomains_init();
        omap44xx_cminst_init();
        am33xx_clockdomains_init();
        am33xx_hwmod_init();
        omap_hwmod_init_postsetup();
        omap3xxx_clk_init();    // 时钟初始化 ---> 接下面clock3xxx_data.c
    }

• 3xxx 时钟初始化

    //  arm/mach-omap2/clock3xxx_data.c
    int __init omap3xxx_clk_init(void)
    {
        struct omap_clk *c;
        u32 cpu_clkflg = 0;
        // ... ...
        } else if (cpu_is_am33xx()) {   // 判断cpu
             am33xx_clk_init();   //  ---- >  接下面  clock33xx_data.c
             return 0;
        // ... ....
        if (cpu_is_omap3630())
            dpll4_dd = dpll4_dd_3630;
        else
            dpll4_dd = dpll4_dd_34xx;

        clk_init(&omap2_clk_functions);
        
        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
             c++)
            clk_preinit(c->lk.clk);
    
        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
             c++)
            if (c->cpu & cpu_clkflg) {
                clkdev_add(&c->lk);
                clk_register(c->lk.clk);
                omap2_init_clk_clkdm(c->lk.clk);
            }
        
        /* Disable autoidle on all clocks; let the PM code enable it later */
            omap_clk_disable_autoidle_all();
            
        recalculate_root_clocks();
        
        pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
            (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
            (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
        
        /*
         * Only enable those clocks we will need, let the drivers
         * enable other clocks as necessary
         */ 
        clk_enable_init_clocks();

        /*
         * Lock DPLL5 -- here only until other device init code can
         * handle this
         */
        if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
            omap3_clk_lock_dpll5();

        /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
        sdrc_ick_p = clk_get(NULL, "sdrc_ick");
        arm_fck_p = clk_get(NULL, "arm_fck");

        return 0;

        // ... ...
    }

• 33xx 时钟的初始化

    // arch/arm/mach-omap2/clock33xx_data.c
    int __init am33xx_clk_init(void)
    {
        struct omap_clk *c;
        u32 cpu_clkflg; 
    
        if (cpu_is_am33xx()) {
            cpu_mask = RATE_IN_AM33XX;
            cpu_clkflg = CK_AM33XX;
        }

        clk_init(&omap2_clk_functions);

        for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
            clk_preinit(c->lk.clk);
        
        for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
            if (c->cpu & cpu_clkflg) {
                clkdev_add(&c->lk);
                clk_register(c->lk.clk);
                omap2_init_clk_clkdm(c->lk.clk);
            }
    
        recalculate_root_clocks();
        
        /*
         * Only enable those clocks we will need, let the drivers
         * enable other clocks as necessary
         */
        clk_enable_init_clocks();
        
        return 0; 
    }