gold序列的verilog实现
摘要:
gold序列产生程序:module gold_sque_gen( rst, clk, delay, gold_out );input rst;input clk;input [11:0] delay;output reg gold_out;reg [11:0] counter;reg [11:0] m1_sequence;reg [11:0] m2_sequence;reg [1:0] state;parameter ready = 2'b00;parameter calcu = 2'b01;always @(posedge clk)begin if(!rst) begin . 阅读全文
posted @ 2012-04-07 14:28 chenfengfei 阅读(1653) 评论(1) 推荐(2) 编辑