摘要： module mxulie( clk, rst, ena, m_out, load ); input clk; input rst; input ena; output reg m_out; output reg load;reg [11:0] shift;always @(posedge clk) begin if(!rst) begin m_out <= 1'b0; load <= 1'b0; shift <= 12'b1111_1111_1111; end else begin if(ena) begin //shift[0] <= ( s 阅读全文