1 `timescale 1ns/1ps
2 module adc_dis(
3 clk ,
4 rst_n ,
5 sm_seg ,
6 sm_bit
7 );
8
9 input clk;//50HZ
10 input rst_n;
11 output[7:0] sm_seg;//段选
12 output[5:0] sm_bit;//位选
13
14 reg [7:0] sm_seg;
15 reg [5:0] sm_bit;
16 reg [31:0] count;
17 reg [31:0] count2;
18 reg [3:0] i;//数码管位数
19 reg clk1, clk2;
20 reg [3:0]ge,shi,bai,qian,wan,swan;
21 reg [7:0] ge_reg,shi_reg,bai_reg,qian_reg,wan_reg,swan_reg;
22
23 parameter//共阳极
24 led_GYA0 = 8'hc0, //'0'
25 led_GYA1 = 8'hf9, //'1'
26 led_GYA2 = 8'ha4, //'2'
27 led_GYA3 = 8'hb0, //'3'
28 led_GYA4 = 8'h99, //'4'
29 led_GYA5 = 8'h92, //'5'
30 led_GYA6 = 8'h82, //'6'
31 led_GYA7 = 8'hf8, //'7'
32 led_GYA8 = 8'h80, //'8'
33 led_GYA9 = 8'h90; //'9'
34
35 /****************分频1S*****************/
36 always@(posedge clk or negedge rst_n) begin
37 if(!rst_n) begin //同步复位
38 clk2 <= 1'b0;
39 count2 <= 32'b0;
40 end
41 else if(count2 == 32'd249999)begin //高低电平转换 5*10^7*20ns=10^9ns=1s
42 clk2 <= ~clk2;
43 count2 <= 32'b0;
44 end
45 else begin
46 count2 <= count2 + 1'b1; //计数
47 end
48 end
49
50 /******************计数*********************/
51 always@(posedge clk2 or negedge rst_n) begin//个位处理
52 if(!rst_n) begin
53 ge <= 4'b0000;
54 shi <= 4'b0000;
55 bai <= 4'b0000;
56 qian <= 4'b0000;
57 wan <= 4'b0000;
58 swan <= 4'b0000;
59 end
60 else if(ge == 4'b1010) begin //个位等于10
61 ge = 4'b0000;
62 shi = shi + 1'b1;
63 if(shi == 4'b1010) begin//十位等于10
64 shi = 4'b0000;
65 bai = bai + 1'b1;
66 if(bai == 4'b1010) begin//百位等于10
67 bai = 4'b0000;
68 qian = qian + 1'b1;
69 if(qian == 4'b1010) begin//千位等于10
70 qian = 4'b0000;
71 wan = wan + 1'b1;
72 if(wan == 4'b1010) begin//万位等于10
73 wan = 4'b0000;
74 swan = swan + 1'b1;
75 if(swan == 4'b1010) begin//十万位等于10
76 ge <= 4'b0000;
77 shi <= 4'b0000;
78 bai <= 4'b0000;
79 qian <= 4'b0000;
80 wan <= 4'b0000;
81 swan <= 4'b0000;
82 end
83 end
84 end
85 end
86 end
87 end
88 else begin
89 ge <= ge + 1'b1;
90 end
91
92 end
93
94 /***************编码*******************/
95 always@(posedge clk2 or negedge rst_n) begin
96 case(ge)
97 4'b0000: ge_reg <= led_GYA0;
98 4'b0001: ge_reg <= led_GYA1;
99 4'b0010: ge_reg <= led_GYA2;
100 4'b0011: ge_reg <= led_GYA3;
101 4'b0100: ge_reg <= led_GYA4;
102 4'b0101: ge_reg <= led_GYA5;
103 4'b0110: ge_reg <= led_GYA6;
104 4'b0111: ge_reg <= led_GYA7;
105 4'b1000: ge_reg <= led_GYA8;
106 4'b1001: ge_reg <= led_GYA9;
107 default: ge_reg <= led_GYA0;
108 endcase
109
110 case(shi)
111 4'b0000: shi_reg <= led_GYA0;
112 4'b0001: shi_reg <= led_GYA1;
113 4'b0010: shi_reg <= led_GYA2;
114 4'b0011: shi_reg <= led_GYA3;
115 4'b0100: shi_reg <= led_GYA4;
116 4'b0101: shi_reg <= led_GYA5;
117 4'b0110: shi_reg <= led_GYA6;
118 4'b0111: shi_reg <= led_GYA7;
119 4'b1000: shi_reg <= led_GYA8;
120 4'b1001: shi_reg <= led_GYA9;
121 default: shi_reg <= led_GYA0;
122 endcase
123
124 case(bai)
125 4'b0000: bai_reg <= led_GYA0;
126 4'b0001: bai_reg <= led_GYA1;
127 4'b0010: bai_reg <= led_GYA2;
128 4'b0011: bai_reg <= led_GYA3;
129 4'b0100: bai_reg <= led_GYA4;
130 4'b0101: bai_reg <= led_GYA5;
131 4'b0110: bai_reg <= led_GYA6;
132 4'b0111: bai_reg <= led_GYA7;
133 4'b1000: bai_reg <= led_GYA8;
134 4'b1001: bai_reg <= led_GYA9;
135 default: bai_reg <= led_GYA0;
136 endcase
137
138 case(qian)
139 4'b0000: qian_reg <= led_GYA0;
140 4'b0001: qian_reg <= led_GYA1;
141 4'b0010: qian_reg <= led_GYA2;
142 4'b0011: qian_reg <= led_GYA3;
143 4'b0100: qian_reg <= led_GYA4;
144 4'b0101: qian_reg <= led_GYA5;
145 4'b0110: qian_reg <= led_GYA6;
146 4'b0111: qian_reg <= led_GYA7;
147 4'b1000: qian_reg <= led_GYA8;
148 4'b1001: qian_reg <= led_GYA9;
149 default: qian_reg <= led_GYA0;
150 endcase
151
152 case(wan)
153 4'b0000: wan_reg <= led_GYA0;
154 4'b0001: wan_reg <= led_GYA1;
155 4'b0010: wan_reg <= led_GYA2;
156 4'b0011: wan_reg <= led_GYA3;
157 4'b0100: wan_reg <= led_GYA4;
158 4'b0101: wan_reg <= led_GYA5;
159 4'b0110: wan_reg <= led_GYA6;
160 4'b0111: wan_reg <= led_GYA7;
161 4'b1000: wan_reg <= led_GYA8;
162 4'b1001: wan_reg <= led_GYA9;
163 default: wan_reg <= led_GYA0;
164 endcase
165
166 case(swan)
167 4'b0000: swan_reg <= led_GYA0;
168 4'b0001: swan_reg <= led_GYA1;
169 4'b0010: swan_reg <= led_GYA2;
170 4'b0011: swan_reg <= led_GYA3;
171 4'b0100: swan_reg <= led_GYA4;
172 4'b0101: swan_reg <= led_GYA5;
173 4'b0110: swan_reg <= led_GYA6;
174 4'b0111: swan_reg <= led_GYA7;
175 4'b1000: swan_reg <= led_GYA8;
176 4'b1001: swan_reg <= led_GYA9;
177 default: swan_reg <= led_GYA0;
178 endcase
179 end
180
181 /****************分频1MS*****************/
182 always@(posedge clk or negedge rst_n) begin
183 if(!rst_n) begin //同步复位
184 clk1 <= 1'b0;
185 count <= 1'b0;
186 end
187 else if(count == 32'd24999)begin //高低电平转换 25000*20=500000ns=0.5ms
188 clk1 <= ~clk1;
189 count <= 1'b0;
190 end
191 else begin
192 count <= count + 1'b1; //计数
193 end
194 end
195
196 /************数码管位数循环****************/
197 always@(posedge clk1 or negedge rst_n) begin
198
199 if(!rst_n) begin //同步复位
200 i <= 4'b0000;
201 end
202 else if(i == 4'b0101) begin
203 i <= 4'b0000;
204 end
205 else begin
206 i <= i + 1'b1;
207 end
208 end
209
210 /************数码管显示****************/
211 always@(posedge clk1 or negedge rst_n) begin
212 case(i)
213 4'b0000: begin sm_seg <= ge_reg; sm_bit <= 6'b11_1110; end
214 4'b0001: begin sm_seg <= shi_reg; sm_bit <= 6'b11_1101; end
215 4'b0010: begin sm_seg <= bai_reg; sm_bit <= 6'b11_1011; end
216 4'b0011: begin sm_seg <= qian_reg; sm_bit <= 6'b11_0111; end
217 4'b0100: begin sm_seg <= wan_reg; sm_bit <= 6'b10_1111; end
218 4'b0101: begin sm_seg <= swan_reg; sm_bit <= 6'b01_1111; end
219 default: begin sm_seg <= led_GYA0; sm_bit <= 6'b11_1111; end
220 endcase
221 end
222
223 endmodule
