（原创）system verilog——uart发送模块的设计

仿真结果如下：

p_start是验证从载入要发送的数据到发送低有效的起始位这段时间的时序是否正确，,p_shift是验证从准备好开始发送到发送过程中

的数据的九次移位是否正确,p_state是跟踪发送过程中状态机的状态。

具体代码如下：

 

  1`timescale 1ns/10ps
  2module uart_tx(din,load,clk,rst,txd,ready,c_state);
  3parameter fifo_sva=1'b1;
  4input [7:0] din;       
  5input load;        
  6input clk;            
  7input rst;             
  8output txd;        
  9output ready;            
 10output [3:0]c_state;        //state output,just for debug
 11
 12logic ready;            //ready status bit
 13logic shift;   //shift bit
 14logic txd;                //transmit bit
 15
 16logic [7:0] hold;            //holding the data
 17logic [8:0] send;   //send bits
 18    
 19//load data
 20always_ff@(posedge clk or posedge rst)
 21begin
 22    if(rst)
 23     hold<=0;
 24    else if(load)
 25     hold<=din;
 26    else 
 27     hold<=hold;
 28end 
 29//ready to send bit
 30always_ff@(posedge clk or posedge rst)
 31begin
 32    if(rst)
 33     ready<=0;
 34    else if(load)
 35     ready<=1;
 36    else 
 37     ready<=0;
 38end
 39
 40//shift and send bit
 41always_ff@(posedge clk or posedge rst)
 42begin
 43    if(rst)begin
 44     send[8:0]<=9'b111111111;
 45     txd<=1'b1;
 46    end
 47    else if(ready)begin
 48     send[8:0]<={hold,1'b0};
 49     txd<=send[0];
 50    end
 51    else if(shift)begin
 52     send[8:0]<={1'b1,send[8:1]};
 53     txd<=send[0];
 54    end
 55    else begin
 56     send<=send;
 57     txd<=send[0];
 58    end
 59end
 60
 61// state machine    
 62parameter [3:0] //synopsys enum STATE_TYPE
 63    UART_IDLE = 4'b0000,
 64    UART_STARTBIT = 4'b0001,
 65    UART_BIT7 = 4'b0010,
 66    UART_BIT6 = 4'b0011,
 67    UART_BIT5 = 4'b0100,
 68    UART_BIT4 = 4'b0101,
 69    UART_BIT3 = 4'b0110,
 70    UART_BIT2 = 4'b0111,
 71    UART_BIT1 = 4'b1000,
 72    UART_BIT0 = 4'b1001,
 73    UART_STOPBIT = 4'b1010;
 74 
 75
 76logic [3:0]  c_state;
 77logic [3:0]  n_state;
 78 
 79 //sequencial logic
 80always_ff @ (posedge clk or posedge rst)
 81begin
 82   if (rst) 
 83      c_state <= UART_IDLE;   
 84   else  
 85      c_state <= n_state;   
 86end
 87//combinational logic
 88always_ff @ (c_state or ready or shift)
 89begin 
 90        case (c_state) //synopsys full_case
 91            UART_IDLE: begin
 92                if (ready ) begin
 93                    n_state <= UART_STARTBIT;
 94                    shift = 0;
 95                end
 96                else begin
 97                    n_state <= UART_IDLE;
 98                    shift = 0;
 99                end
            end 
            UART_STARTBIT: begin
                    n_state <= UART_BIT7;    
                    shift = 1;    
                end
            UART_BIT7: begin
                if(shift) begin
                    n_state <= UART_BIT6;    
                    shift = 1;            
                end
                else begin
                    n_state <= UART_BIT7;    
                    shift = 0;
                end
            end
            UART_BIT6: begin
                if(shift) begin
                    n_state <= UART_BIT5;    
                    shift = 1;            
                end
                else begin
                    n_state <= UART_BIT6;        
                    shift = 0;
                end
            end
            UART_BIT5: begin
                if(shift) begin
                    n_state <= UART_BIT4;        
                    shift = 1;            

                end
                else begin
                    n_state <= UART_BIT5;    
                    shift = 0;
                end
            end
            UART_BIT4: begin
                if(shift) begin
                    n_state <= UART_BIT3;    
                    shift = 1;            

                end
                else begin
                    n_state <= UART_BIT4;        
                    shift = 0;
                end
            end
            UART_BIT3: begin
                if(shift) begin
                    n_state <= UART_BIT2;    
                    shift = 1;        
                end
                else    begin
                    n_state <= UART_BIT3;    
                    shift = 0;
                end
            end
            UART_BIT2: begin
                if(shift) begin
                    n_state <= UART_BIT1;    
                    shift = 1;            

                end
                else begin
                    n_state <= UART_BIT2;        
                    shift = 0;
                end
            end
            UART_BIT1: begin
                if(shift) begin
                    n_state <= UART_BIT0;    
                    shift = 1;            
                end
                else begin
                    n_state <= UART_BIT1;        
                    shift = 0;
                end
            end
            UART_BIT0: begin
                if(shift) begin
                    n_state <= UART_STOPBIT;    
                    shift = 1;        
                end
                else begin
                    n_state <= UART_BIT0;        
                    shift = 0;
                end
            end
            UART_STOPBIT: begin
                if(!ready) begin
                    n_state <= UART_IDLE;    
                    shift = 0;            
                end
                else if (ready) begin
                    n_state <= UART_STARTBIT;
                    shift = 0;            
                end
                else begin
                    n_state <= UART_STOPBIT;
                    shift = 0;            
                end
             end
            default: begin
                  n_state <= UART_IDLE;
                   shift = 0;                    
            end 
      endcase
end 


//sva sequence description
sequence s_state;
(c_state==UART_STARTBIT) ##1(c_state==UART_BIT7) 
##1(c_state==UART_BIT6) ##1(c_state==UART_BIT5) 
##1(c_state==UART_BIT4) ##1(c_state==UART_BIT3) 
##1(c_state==UART_BIT2) ##1(c_state==UART_BIT1) 
##1(c_state==UART_BIT0) ##1(c_state==UART_STOPBIT);
endsequence
//sva property description
property p_start; 
 @(posedge clk)
  load|=>ready ##2!txd;  
endproperty
property p_state; 
 @(posedge clk)
 ((!rst)&&ready)|=>s_state;
endproperty
property p_shift; 
 @(posedge clk)
 ((!rst)&&ready)|=>(shift[*9]); 
endproperty

//sva check
always_ff@(posedge clk)
if(fifo_sva)
begin
a_start:assert property(p_start)           
        else $display("start error at %d !",$time);
a_state:assert property(p_state)
        else $display("state machine error at %d !",$time);
a_shift:assert property(p_shift)
        else $display("shift error at %d !",$time);    
c_start:cover property(p_start);
c_c_state:cover property(p_state);
c_shift:cover property(p_shift);
end
endmodule

 

testbench如下：

 

 1`timescale 1ns/10ps
 2module uart_tx_testbench; 
 3    logic [7:0] din;
 4    logic load;
 5    logic clk;
 6    logic rst;
 7    wire txd;
 8    wire ready;
 9    wire[3:0] c_state;
uart_tx  #(1)
     uart_tx_inst(
                  .din(din),
                  .load(load),
                  .clk(clk),
                  .rst(rst),
                  .txd(txd),
                  .ready(ready),
                  .c_state(c_state)
);
parameter p=10;
initial
begin
   clk=1;
   rst=1;
   load=0;
#1 rst=0;
#p load=1;
   din=8'b10101010;
#p load=0;
#p ;#p ;#p ;#p ;#p ;#p ;#p ;#p ;
#p ;#p ;#p ;#p ;#p ;#p ;#p ;#p ;
#p load=1;
   din=8'b11001100;
#p load=0;
#p ;#p ;#p ;#p ;#p ;#p ;#p ;#p ;
#p load=1;
   din=8'b11110000;
#p load=0;
#1000 $finish;
end
initial
begin
$monitor("din=%b,txd=%b,time=%d",din,txd,$time);
end
always #5 clk=~clk;
endmodule

 

以上代码都已通过调试，调试环境为modelsim6.3f