（原创）uart发送数据模块设计

我们可以发送任意八位数据din，din之间可以间隔任何时间，只要模块接受到新的din数据，就会以固定的频率

一个接一个的将数据发出。仿真波形如下：

 

  1module uart_tx(din,load,clk,rst,txd,ready,c_state);
  2input [7:0] din;        //data to be transmitted    
  3input load;            //loads the transmit register
  4input clk;            // 1x transmit clock
  5input rst;             // resets the registers
  6output txd;            // output data
  7output ready;            // indicates ready to recieve char to transmit
  8output [3:0]c_state;        //state output,just for debug
  9
 10reg ready;            //ready status bit
 11reg shift;   //shift bit
 12reg txd;                //transmit bit
 13
 14reg [7:0] hold;            //holding register for the data
 15reg [8:0] send;   //send bits
 16    
 17//load data
 18always@(posedge clk or posedge rst)
 19begin
 20    if(rst)
 21     hold<=0;
 22    else if(load)
 23     hold<=din;
 24    else 
 25     hold<=hold;
 26end 
 27//ready to send bit
 28always@(posedge clk or posedge rst)
 29begin
 30    if(rst)
 31     ready<=0;
 32    else if(load)
 33     ready<=1;
 34    else 
 35     ready<=0;
 36end
 37
 38//shift and send bit
 39always@(posedge clk or posedge rst)
 40begin
 41    if(rst)begin
 42     send[8:0]<=9'b111111111;
 43     txd<=1'b1;
 44    end
 45    else if(ready)begin
 46     send[8:0]<={hold,1'b0};
 47     txd<=send[0];
 48    end
 49    else if(shift)begin
 50     send[8:0]<={1'b1,send[8:1]};
 51     txd<=send[0];
 52    end
 53    else begin
 54     send<=send;
 55     txd<=send[0];
 56    end
 57end
 58
 59// state machine    
 60parameter [3:0] //synopsys enum STATE_TYPE
 61    UART_IDLE = 4'b0000,
 62    UART_STARTBIT = 4'b0001,
 63    UART_BIT7 = 4'b0010,
 64    UART_BIT6 = 4'b0011,
 65    UART_BIT5 = 4'b0100,
 66    UART_BIT4 = 4'b0101,
 67    UART_BIT3 = 4'b0110,
 68    UART_BIT2 = 4'b0111,
 69    UART_BIT1 = 4'b1000,
 70    UART_BIT0 = 4'b1001,
 71    UART_STOPBIT = 4'b1010;
 72 
 73
 74reg [3:0]  c_state;
 75reg [3:0]  n_state;
 76 
 77 //sequencial logic
 78always @ (posedge clk or posedge rst)
 79begin
 80   if (rst) 
 81      c_state <= UART_IDLE;   
 82   else  
 83      c_state <= n_state;   
 84end
 85//combinational logic
 86always @ (c_state or ready or shift)
 87begin 
 88        case (c_state) //synopsys full_case
 89            UART_IDLE: begin
 90                if (ready ) begin
 91                    n_state <= UART_STARTBIT;
 92                    shift = 0;
 93                end
 94                else begin
 95                    n_state <= UART_IDLE;
 96                    shift = 0;
 97                end
 98            end 
 99            UART_STARTBIT: begin
                    n_state <= UART_BIT7;    
                    shift = 1;    
                end
            UART_BIT7: begin
                if(shift) begin
                    n_state <= UART_BIT6;    
                    shift = 1;            
                end
                else begin
                    n_state <= UART_BIT7;    
                    shift = 0;
                end
            end
            UART_BIT6: begin
                if(shift) begin
                    n_state <= UART_BIT5;    
                    shift = 1;            
                end
                else begin
                    n_state <= UART_BIT6;        
                    shift = 0;
                end
            end
            UART_BIT5: begin
                if(shift) begin
                    n_state <= UART_BIT4;        
                    shift = 1;            

                end
                else begin
                    n_state <= UART_BIT5;    
                    shift = 0;
                end
            end
            UART_BIT4: begin
                if(shift) begin
                    n_state <= UART_BIT3;    
                    shift = 1;            

                end
                else begin
                    n_state <= UART_BIT4;        
                    shift = 0;
                end
            end
            UART_BIT3: begin
                if(shift) begin
                    n_state <= UART_BIT2;    
                    shift = 1;        
                end
                else    begin
                    n_state <= UART_BIT3;    
                    shift = 0;
                end
            end
            UART_BIT2: begin
                if(shift) begin
                    n_state <= UART_BIT1;    
                    shift = 1;            

                end
                else begin
                    n_state <= UART_BIT2;        
                    shift = 0;
                end
            end
            UART_BIT1: begin
                if(shift) begin
                    n_state <= UART_BIT0;    
                    shift = 1;            
                end
                else begin
                    n_state <= UART_BIT1;        
                    shift = 0;
                end
            end
            UART_BIT0: begin
                if(shift) begin
                    n_state <= UART_STOPBIT;    
                    shift = 1;        
                end
                else begin
                    n_state <= UART_BIT0;        
                    shift = 0;
                end
            end
            UART_STOPBIT: begin
                if(!ready) begin
                    n_state <= UART_IDLE;    
                    shift = 0;            
                end
                else if (ready) begin
                    n_state <= UART_STARTBIT;
                    shift = 0;            
                end
                else begin
                    n_state <= UART_STOPBIT;
                    shift = 0;            
                end
             end
            default: begin
                  n_state <= UART_IDLE;
                   shift = 0;                    
            end 
      endcase
end 
endmodule

 

 1module uart_tx_testbench; 
 2    reg [7:0] din;
 3    reg load;
 4    reg clk;
 5    reg rst;
 6    wire txd;
 7    wire ready;
 8    wire[3:0] c_state;
 9uart_tx uart_tx_inst(
                  .din(din),
                  .load(load),
                  .clk(clk),
                  .rst(rst),
                  .txd(txd),
                  .ready(ready),
                  .c_state(c_state)
);
parameter p=10;
initial
begin
   clk=0;
   rst=1;
   load=0;
#1 rst=0;
#p load=1;
   din=8'b10101010;
#p load=0;
#p ;#p ;#p ;#p ;#p ;#p ;#p ;#p ;
#p ;#p ;#p ;#p ;#p ;#p ;#p ;#p ;
#p load=1;
   din=8'b11001100;
#p load=0;
#p ;#p ;#p ;#p ;#p ;#p ;#p ;#p ;
#p load=1;
   din=8'b11110000;
#p load=0;
#1000 $finish;
end
initial
begin
$monitor("din=%b,txd=%b,time=%d",din,txd,$time);
end
always #5 clk=~clk;
endmodule