Shift Register(Using Submodule)
摘要：/***************************************************/ Shift Register module by Submodule/ Programing by seongki***************************************...
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2014-10-02 21:22
YB-Park
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Shift Register
摘要：/***************************************************/ Shift Register module/ Programing by seongki***************************************************/...
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2014-10-02 21:18
YB-Park
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Blocking & Nonblocking module
摘要：/***************************************************/ Blocking and Nonblocking circuit and Simulation/ Using level sensitive event/ Programing by seon...
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2014-10-02 21:11
YB-Park
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Verilog HDL test bench 문법에 관한
摘要：16bit ripple carry adder test bench`timescale 1ns/1nsmodule testbench2;reg [15:0] a, [15:0] b, c_in;wire [15:0] sum, c_out;fulla16 adder(.[15:0] a([15...
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2014-09-25 13:57
YB-Park
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ModelSim6.2 설치에 관한(About the Installation problem of ModelSim 6.2)
摘要：ModelSim 설치는 PC OS 따라서 호환성 문제가 발생한다.!!!!!! Vista OS에서는 ModelSim 설치가 안됨(호환성 문제)XP, Win7에서는 호환성 문제 없음!
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2014-09-25 13:50
YB-Park
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4비트,16비트 가산기에 관한 문제(계층설계)
摘要：Q: 수업듣는 학생의 질문1. half-addermodule half_adder (S, C, x, y);output S, C;input x, y;xor (S, x, y);and (C, x, y);endmodule2. full-addermodule full_adder (...
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2014-09-25 13:30
YB-Park
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