Notes of "The Unbridged Pentium 4" - Overview of the Processor Role

1.  All IA32 processors up to and including the Pentium processor use variable length(1~15bytes) instructions, all IA32 processors starting with the Pentium Pro translate the IA32 instructions into primitive fixed-length instrucitons prior to executing them. These instructions are refered to as micro-ops, or miu-ops.

2. Processor Activities at Startup:

• Fetches and executes the system's Power-On Self-Test(POST) program from the ROM.
• Reads the OS loader program from mass storage.
• Executes the OS loader program which loads the remainder of the OS kernel (Control transfer)
• Executes the OS kernel startup code which completes the setup of the OS adn loads the loadable device drivers into memory. The OS calls the driver's initialization code to complete the setup of the associated device.

3. Processor Activities During Run-Time:

• Load and Run Application Programs.
• Application Program Calls the OS (suspend application - switch to OS - resume application)
• Handling External Hardware Interrupts (suspend program - jump to interrupt handler - resume program)
• Calling a Device Driver (program -> OS -> device driver)
• Handling Software Exceptions (jumps to exception handler, fix the problem, reattempt execution of the instruction)

4. System Overview: (Pentium 4 845D Chipset)

• Pentium 4 Processor
• Memory Control Hub(MCH): (connect with the ICH by the high speed, 11-bit Hub Interface(HI)link)
  incorporates the system memory controller
  provides the interface between the AGP device and system memory via the point-to-point AGP(Acceerated Graphics Port)
  interfaces the processor's FSB to the AGP bus and to the system memory bus
  provides the interface to system memory for all system devices through the ICH
• IO Control Hub(ICH):
  integrated Ethernet LAN controller connect to the network via the LCI(LAN Controller Interface)
  integrated IDE Controller
  integrated USB 1.1-compatible host controller
  Hub link to PCI bus interface
  integrated PCI bus arbiter supports up to five PCI card slots
  integrated System Management Bus(SMBus) interface permits the currently-running program to access the processor's internal Processor Information ROM(PIROM) as well as the processor's internal Thermal Diode
  Low-Pin Count(LPC) bus interface permits connection to legacy PC devices(parallel port, COM pors, floppy drive, keyboard, mouse)
  BIOS ROM interface (FWH(Firmware to Hub Link)interface)
  Audio Codec(AC)'97 Link (on-board Audio Codec, Communication and Networking Riser(CNR)connector)
  integrated LAN interface (10/100 Ethernet interface)
  integrated IO APIC(Advanced Programmable Interrupt Controller) (deliver interrupts from hardware devices to the processors in a multiple processor environment)
  integrated legacy dual-8259a interrupt controllers (deliver interrupts to the processor in a single processor system)
• Super IO(SIO) Chip: connect to ICH via LPC interface, incorporates the legacy devices(parallel port, COM pors, floppy drive, keyboard, mouse)
• DDR RAM: Double-Data Rate RAM
• IDE RAID Controller: embedded IDE RAID(Redundant Array of Inexpensive Drives) controller, acting as a PCI bus master, transfer disk data dirctly to and from system memory over the PCI bus and the Hub Interface
• USB 2.0 Controller: embedded USB2.0 controller, acting as a PCI bus master, transfer data to and from system memory over the PCI bus and the Hub Interface
• Five PCI Card Slots