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2005年5月27日

摘要: 1. PCI Express the Root Complex plays the role that used to be played by the Memory Control Hub(MCH), or the North Bridge. It also incorporates te system memory controller (rather than residing the sy... 阅读全文

posted @ 2005-05-27 15:51 bullfinch 阅读(504) 评论(0) 推荐(0) 编辑

摘要: Tabe 1 The Pentium 4 Roadmap (Description omitted) Code Name Date The Pentium 4 Processor Willamette 11/20/00 Northwood 01/07/02 Northwood B with Hyper-Threading 11/14/02 Northw... 阅读全文

posted @ 2005-05-27 14:19 bullfinch 阅读(422) 评论(0) 推荐(0) 编辑

摘要: 1. All IA32 processors up to and including the Pentium processor use variable length(1~15bytes) instructions, all IA32 processors starting with the Pentium Pro translate the IA32 instructions into pr... 阅读全文

posted @ 2005-05-27 13:52 bullfinch 阅读(617) 评论(0) 推荐(0) 编辑

2005年5月15日

摘要: 1. The Pentium processor address bus consits of two sets of signal lines: the address bus proper, consisting of 29 signal lines designated A31:A3. the Byte Enable bus, consisting of the 8 signal line... 阅读全文

posted @ 2005-05-15 23:34 bullfinch 阅读(814) 评论(0) 推荐(0) 编辑

摘要: Single Processor MESI Implementation: Initial Read from System Memory: (II)[SE] L2-E L2-WB/WT#=0 L1-S First Write to the Internal Cache Line: (SE)[EM] L2-M L2-WB/WT#=1 L1-E (Write-Onc... 阅读全文

posted @ 2005-05-15 17:56 bullfinch 阅读(671) 评论(0) 推荐(0) 编辑