测频2
fpga通过pll倍频产生200M时钟,来测量高频率信号源,不知道为啥加到500M就有问题了,测量的fx比实际值要小,正常的话每一兆有3hz的误差,40M的话大约有120Hz的误差,满足2015年产生10-4的要求,贴一下代码。
module pinlv( //system interface input clk, input rst_n, //sig interface input sig_in, //user interface output reg [31:0] pinlv ); parameter F_1S = 199_999_999; //200M //fgate reg fgate; reg [31:0] fgate_cnt; always @(posedge clk or negedge rst_n) begin if(!rst_n) fgate_cnt <= 0; else if(fgate_cnt >= F_1S) fgate_cnt <= 0; else fgate_cnt <= fgate_cnt + 1; end always @(posedge clk or negedge rst_n) begin if(!rst_n) fgate <= 0; else if(fgate_cnt >= F_1S) fgate <= ~fgate; else fgate <= fgate; end //fact gate reg start_cnt; always @(posedge sig_in) begin if(fgate) start_cnt <= 1; else start_cnt <= 0; end //fx++ reg [31:0] fx_cnt_temp; always @(posedge sig_in or negedge rst_n) begin if(!rst_n) fx_cnt_temp <= 0; else if(start_cnt) fx_cnt_temp <= fx_cnt_temp + 1; else fx_cnt_temp <= 0; end //锁存 always @(negedge start_cnt) begin pinlv <= fx_cnt_temp; end endmodule