distributor之Interrupt Set/Clear-Active Registers, GICD_IS/CACTIVERn
set active寄存器。顾名思义就是把一个中断置为active状态,clear active寄存器就是清除active状态,在这里我们有必要说明一下中断状态的一些概念:
active状态:假设此时处理器正在处理这个中断的处理函数。那么我们能够说此时这个中断处于active状态。
pending状态:假设此时一个中断已经产生,可是处理器还未处理,那么我们能够说此时这个中断处于pending状态;
inactive状态:假设一个中断既不是active状态也不是pending状态,那么就称之为处于inactive状态;
active and pending状态:假设处理器正在运行一个中断的处理函数。此时这个中断的中断源又产生了一个中断,那么我们称之为此中断处于active and pending状态;
对于set active寄存器,写1有效,写0无效;读出来的值表示active状态。假设是1,表示此时此中断处于active状态。此寄存器相对于distributor的偏移区间为0x300-0x37C 。计算方法为:
For interrupt IDm, when DIV and MOD are the integer division and modulo operations:
the corresponding GICD_ISACTIVERn number,n, is given byn = m DIV 32
the offset of the required GICD_ISACTIVERn is (0x300+
(4*n))
the bit number of the required Set-active bit in this register is mMOD 32.
For interrupt IDm, when DIV and MOD are the integer division and modulo operations:
the corresponding GICD_ICACTIVERn number,n, is given byn = m DIV 32
the offset of the required GICD_ICACTIVERn is (0x380+
(4*n))
the bit number of the required Clear-active bit in this register is mMOD 32.