10

2012年6月7日

时钟系统

摘要： 时序分析——公共时钟（内同步，外同步），源同步 时钟系统可以分为公共时钟和源同步时钟，公共同步又可以分为内同步和外同步，内同步典型的即为CPU与SDRAM系统的读写。 建立时间：要求接收端的数据信号必须先于时钟信号到达。时钟信号的延时：Tdelay = Tco_clka + Tflt_clka4 数据信号的延时：Tdata_delay = Tco_clkb + Tflt_clkb + Tco... 阅读全文

posted @ 2012-06-07 15:40 believe 阅读(583) 评论(0) 推荐(0) 编辑

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/* * Name: SyntaxHighlighter.brushes.Verilog * Author: Yuphone Chang * Email: yuphone@qq.com/ * Create Date: 5.18, 2010 */ SyntaxHighlighter.brushes.Verilog = function() { var datatypes = 'reg integar unsigned ' + 'wire tri wand triand tri0 tri1 supply0 supply1 trireg ' + 'parameter specparam defparam event '; var primitives = 'and nand or nor xor xnor ' + 'buf not ' + 'bufif0 bufif1 notif0 notif1 ' 'pullup pulldown ' + 'pmos rpmos nmos rnmos '; var keywords = 'module endmodule ' + 'input output inout ' + 'begin end ' + 'assign deassign always initial genvar ' + 'forever repeat disable wait ' + 'function endfunction' + 'task ' + 'endtask ' + 'generate endgenerate ' + 'specify endspecify ' + 'posedge negedge ' + 'if else for while ' + 'case casex casez endcase default ' + 'include timescale ' + 'ifdef endif ' + 'celldefine endcelldefine ' + 'attribute ' 'fork join '; var functions = 'display displayb displayo displayh ' + 'write writeb writeo writeh ' + 'strobe strobeb strobeh strobeo ' + 'monitor monitorb monitoro monitorh ' + 'fopen fclose ' + 'readmemb readmemh ' + 'finish stop ' + 'time stime realtime timeformat ' + 'printtimescale ' + 'setup hold setuphold skew recovery period width '; this.regexList = [ // one line comments { regex: SyntaxHighlighter.regexLib.singleLineCComments,css: 'comments' }, // multiline comments { regex: SyntaxHighlighter.regexLib.multiLineCComments, css: 'comments' }, // double quoted strings { regex: SyntaxHighlighter.regexLib.doubleQuotedString, css: 'string' }, // single quoted strings { regex: SyntaxHighlighter.regexLib.singleQuotedString, css: 'string' }, // constants { regex: new RegExp("[0-9]+['][bBoOdDhHeEfFtT][0-9a-fA-FzZxX_]+", 'g'), css: 'constants' }, // datatypes { regex: new RegExp(this.getKeywords(datatypes), 'gm'), css: 'color1 bold' }, // primitives { regex: new RegExp(this.getKeywords(primitives), 'gm'), css: 'color2 bold' }, // keywords { regex: new RegExp(this.getKeywords(keywords), 'gm'), css: 'keyword bold' }, // functions { regex: new RegExp(this.getKeywords(functions), 'gm'), css: 'functions bold' } ]; }; SyntaxHighlighter.brushes.Verilog.prototype = new SyntaxHighlighter.Highlighter(); SyntaxHighlighter.brushes.Verilog.aliases = ['verilog', 'v'];