FSM in verilog

Finite State Machines
.Design methodology for sequential logic
  -- identify distinct states
  -- create state transition diagram
  -- choose state encoding
  -- write combinational Verilog for next-state logic
  -- write combinational Verilog for output signals


FSM的设计方法：
  . 找出组成状态机的单个状态
  . 建立状态转换图（或转换表)
  . 选择状态编码（有几种编码方式,  one-shoot ...)
  . 为转换后的新状态写组合逻辑verilog
  . 为输出信号写组合逻辑verilog