uboot arm cache 知识点简介

一、在uboot ARM版本的start.S中你常常会看到下面的代码：

mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
bic r0, r0, #0x1               @clear bit[0]，disable MMU
mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register

上面代码的意思是：读取c1 到 r0, 然后将r0的一些bit置位或清零。然后将r0写回c1。

c1中的bit是如下面定义的:  见《DDI0406C_C_arm_architecture_reference_manual.pdf》 1707页。

bit[0] MMU enabled or disabled;

bit[2] Data and unified caches enabled or disabled;

bit[3] disable/enable 写入缓冲;

bit[12] Instruction caches enabled  or disabled;

二、c7

 c7比较特殊是wirte only register.

　　MCR p15, 0, <Rd>, c7, <CRm>, op

　　例如：

　　 mcr p15, 0, r0, c7, c5, 0  @清空整个指令cache，详细见《arm体系结构与编程》 205页。

　　MCR p15, 0, <Rt>, c7, c5, 0 ; ICIALLU, Instruction cache invalidate all to PoU. Ignores Rt value.

MCR p15, 0, <Rt>, c7, c5, 0 Invalidate all instruction caches to PoU, invalidate branch predictors a
MCR p15, 0, <Rt>, c7, c5, 1 Invalidate instruction caches by MVA to PoUa
MCR p15, 0, <Rt>, c7, c5, 7 Invalidate MVA from branch predictor
MCR p15, 0, <Rt>, c7, c10, 1 Clean data or unified cache line by MVA to point of coherencyb
MCR p15, 0, <Rt>, c7, c10, 2 Clean data or unified cache line by set/wayb
MCR p15, 0, <Rt>, c7, c11, 1 Clean data or unified cache line by MVA to point of unificationb
MCR p15, 0, <Rt>, c7, c1, 0 Invalidate entire instruction cache Inner Shareablec
MCR p15, 0, <Rt>, c7, c1, 6 Invalidate all branch predictors Inner Shareablec

 

三、c8

这个协处理器是和TLB相关的。

MCR p15, 0, <Rt>, c8, c5, 0 ; ITLBIALL, Instruction TLB invalidate all. Operation ignores Rt value.