vivado中未分配引脚的时序处理方法(转)

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

将这三句添加到时序约束文件（没有创建一个），即可解决Vivado未分配引脚约束报错的问题
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原文链接：https://blog.csdn.net/qq_36248682/article/details/105300860

set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]

以上语句三选一，怎么选看实际需求。通常我都选最后一条，未使用引脚悬空。
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版权声明：本文为CSDN博主「请叫我冻冻」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/dimples_Song/article/details/81326747

[DRC UCIO-1] Unconstrained Logical Port: 12 out of 161 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SPI_1_0_ss1_o, SPI_1_0_ss2_o, SPI_0_0_ss1_o, SPI_0_0_ss2_o, SDIO_0_0_busvolt[2:0], SDIO_0_0_buspow, SDIO_0_0_cdn, SDIO_0_0_clk_fb, SDIO_0_0_led, and SDIO_0_0_wp.