Verilog: Week1 Class1和Modelsim仿真详细步骤

Project:  Intro_Top

1. 1.工程结构:

Intro_Top.v

module Intro_Top
(output X,Y,Z,
 input A,B,C,D);
 
 wire ab,bc,q,qn;
 
 assign #1 Z= ~qn;
 
 AndOr InputCombo01 (.X(ab),.Y(bc),.A(A),.B(B),.C(C));
 SR SRLatch01 (.Q(q),.Qn(qn),.S(bc),.R(D));
 XorNor OutputCombo01 (.X(X),.Y(Y),.A(ab),.B(q),.C(qn));
endmodule

AndOr

AndOr.v

module AndOr 
(output X,Y, input A,B,C);

 assign #10 X = A & B;
 assign #10 Y = B | C;
 
 endmodule

SR

SR.v

module SR (output Q, Qn, input S, R);
 wire q, qn;
 
 assign #1 Q = q;
 assign #1 Qn = qn;
 
 assign #10 q = ~(S & qn);
 assign #10 qn = ~(R & q);
 
 endmodule

XorNor

XorNor.v

module XorNor 
 (output X,Y, input A,B,C);
 
 wire x;
 assign #1 X = x;
 assign #10 x = A ^ B;
 assign #10 Y = ~(X | C);
 
 endmodule

2.测试文件(测试文件不能加到工程里,只能单独设置):

Intro_Top_testbench

Intro_Top_testbench.v

`timescale 1 ns/ 1ns
module Intro_Top_testbench();

reg Astim,Bstim,Cstim,Dstim;
                                               
wire Xwatch,Ywatch,Zwatch;

initial                                                
begin           
   // Each ‘#’ precedes a delay time increment, here in 1 ns units:                                      
    #1 Astim = 1'b0;
    #1 Bstim = 1'b0;
    #1 Cstim = 1'b0;
    #50 Dstim = 1'b1;
    #50 Astim = 1'b0;
    #50 Bstim = 1'b0;
    #50 Cstim = 1'b0;
    //#50 $finish;  // Terminates simulation 50 ns after the last stimulus.
    
end         

Intro_Top i1 (   
    .A(Astim),.B(Bstim),.C(Cstim),.D(Dstim),
    .X(Xwatch),.Y(Ywatch),.Z(Zwatch)
);

endmodule

3.使用Modelsim-Altera进行仿真

并且必须在所有文件中加上`timescale 1 ns/ 1ns！！！

结束。