PLX9030 Operation How To
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1 /* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */
2 /*
3 * (C) Copyright 2002-2003
4 * Josef Wagner, MicroSys GmbH, wagner@microsys.de.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 * Date Modification by
25 * ------- ---------------------------------------------- ---
26 * 30sep02 converted from VxWorks to LINUX wa
27 */
28
29
30 /*
31 DESCRIPTION
32
33 This is the configuration module for the PLX9030 PCI to Local Bus Bridge.
34 It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local
35 registers (CS3) on CPC45.
36 */
37
38 /* includes */
39
40 #include <common.h>
41 #include <malloc.h>
42 #include <net.h>
43 #include <asm/io.h>
44 #include <pci.h>
45
46 /* imports */
47
48
49 /* defines */
50 #define PLX9030_VENDOR_ID 0x10B5
51 #define PLX9030_DEVICE_ID 0x9030
52
53 #undef PLX_DEBUG
54
55 /* PLX9030 register offsets */
56 #define P9030_LAS0RR 0x00
57 #define P9030_LAS1RR 0x04
58 #define P9030_LAS2RR 0x08
59 #define P9030_LAS3RR 0x0c
60 #define P9030_EROMRR 0x10
61 #define P9030_LAS0BA 0x14
62 #define P9030_LAS1BA 0x18
63 #define P9030_LAS2BA 0x1c
64 #define P9030_LAS3BA 0x20
65 #define P9030_EROMBA 0x24
66 #define P9030_LAS0BRD 0x28
67 #define P9030_LAS1BRD 0x2c
68 #define P9030_LAS2BRD 0x30
69 #define P9030_LAS3BRD 0x34
70 #define P9030_EROMBRD 0x38
71 #define P9030_CS0BASE 0x3C
72 #define P9030_CS1BASE 0x40
73 #define P9030_CS2BASE 0x44
74 #define P9030_CS3BASE 0x48
75 #define P9030_INTCSR 0x4c
76 #define P9030_CNTRL 0x50
77 #define P9030_GPIOC 0x54
78
79 /* typedefs */
80
81
82 /* locals */
83
84 static struct pci_device_id supported[] = {
85 { PLX9030_VENDOR_ID, PLX9030_DEVICE_ID },
86 { }
87 };
88
89 /* forward declarations */
90 void sysOutLong(ulong address, ulong value);
91
92
93 /***************************************************************************
94 *
95 * Plx9030Init - init CS0..CS3 for CPC45
96 *
97 *
98 * RETURNS: N/A
99 */
100
101 void Plx9030Init (void)
102 {
103 pci_dev_t devno;
104 ulong membaseCsr; /* base address of device memory space */
105 int idx = 0; /* general index */
106
107
108 /* find plx9030 device */
109
110 if ((devno = pci_find_devices(supported, idx++)) < 0)
111 {
112 printf("No PLX9030 device found !!\n");
113 return;
114 }
115
116
117 #ifdef PLX_DEBUG
118 printf("PLX 9030 device found ! devno = 0x%x\n",devno);
119 #endif
120
121 membaseCsr = PCI_PLX9030_MEMADDR;
122
123 /* set base address */
124 pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr);
125
126 /* enable mapped memory and IO addresses */
127 pci_write_config_dword(devno,
128 PCI_COMMAND,
129 PCI_COMMAND_MEMORY |
130 PCI_COMMAND_MASTER);
131
132
133 /* configure GBIOC */
134 sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */
135
136 /* configure CS0 (SRAM) */
137 sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */
138 sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */
139 sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */
140 sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */
141 /* remap CS0 (SRAM) */
142 pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
143
144 /* configure CS1 (ST16552 / CHAN A) */
145 sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */
146 sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */
147 sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */
148 sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */
149 /* remap CS1 (ST16552 / CHAN A) */
150 /* remap CS1 (ST16552 / CHAN A) */
151 pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
152
153 /* configure CS2 (ST16552 / CHAN B) */
154 sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */
155 sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */
156 sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */
157 sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */
158 /* remap CS2 (ST16552 / CHAN B) */
159 pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
160
161 /* configure CS3 (BCSR) */
162 sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */
163 sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */
164 sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */
165 sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */
166 /* remap CS3 (DISPLAY and BCSR) */
167 pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
168 }
169
170 void sysOutLong(ulong address, ulong value)
171 {
172 *(ulong*)address = cpu_to_le32(value);
173 }
174
2 /*
3 * (C) Copyright 2002-2003
4 * Josef Wagner, MicroSys GmbH, wagner@microsys.de.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 * Date Modification by
25 * ------- ---------------------------------------------- ---
26 * 30sep02 converted from VxWorks to LINUX wa
27 */
28
29
30 /*
31 DESCRIPTION
32
33 This is the configuration module for the PLX9030 PCI to Local Bus Bridge.
34 It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local
35 registers (CS3) on CPC45.
36 */
37
38 /* includes */
39
40 #include <common.h>
41 #include <malloc.h>
42 #include <net.h>
43 #include <asm/io.h>
44 #include <pci.h>
45
46 /* imports */
47
48
49 /* defines */
50 #define PLX9030_VENDOR_ID 0x10B5
51 #define PLX9030_DEVICE_ID 0x9030
52
53 #undef PLX_DEBUG
54
55 /* PLX9030 register offsets */
56 #define P9030_LAS0RR 0x00
57 #define P9030_LAS1RR 0x04
58 #define P9030_LAS2RR 0x08
59 #define P9030_LAS3RR 0x0c
60 #define P9030_EROMRR 0x10
61 #define P9030_LAS0BA 0x14
62 #define P9030_LAS1BA 0x18
63 #define P9030_LAS2BA 0x1c
64 #define P9030_LAS3BA 0x20
65 #define P9030_EROMBA 0x24
66 #define P9030_LAS0BRD 0x28
67 #define P9030_LAS1BRD 0x2c
68 #define P9030_LAS2BRD 0x30
69 #define P9030_LAS3BRD 0x34
70 #define P9030_EROMBRD 0x38
71 #define P9030_CS0BASE 0x3C
72 #define P9030_CS1BASE 0x40
73 #define P9030_CS2BASE 0x44
74 #define P9030_CS3BASE 0x48
75 #define P9030_INTCSR 0x4c
76 #define P9030_CNTRL 0x50
77 #define P9030_GPIOC 0x54
78
79 /* typedefs */
80
81
82 /* locals */
83
84 static struct pci_device_id supported[] = {
85 { PLX9030_VENDOR_ID, PLX9030_DEVICE_ID },
86 { }
87 };
88
89 /* forward declarations */
90 void sysOutLong(ulong address, ulong value);
91
92
93 /***************************************************************************
94 *
95 * Plx9030Init - init CS0..CS3 for CPC45
96 *
97 *
98 * RETURNS: N/A
99 */
100
101 void Plx9030Init (void)
102 {
103 pci_dev_t devno;
104 ulong membaseCsr; /* base address of device memory space */
105 int idx = 0; /* general index */
106
107
108 /* find plx9030 device */
109
110 if ((devno = pci_find_devices(supported, idx++)) < 0)
111 {
112 printf("No PLX9030 device found !!\n");
113 return;
114 }
115
116
117 #ifdef PLX_DEBUG
118 printf("PLX 9030 device found ! devno = 0x%x\n",devno);
119 #endif
120
121 membaseCsr = PCI_PLX9030_MEMADDR;
122
123 /* set base address */
124 pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr);
125
126 /* enable mapped memory and IO addresses */
127 pci_write_config_dword(devno,
128 PCI_COMMAND,
129 PCI_COMMAND_MEMORY |
130 PCI_COMMAND_MASTER);
131
132
133 /* configure GBIOC */
134 sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */
135
136 /* configure CS0 (SRAM) */
137 sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */
138 sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */
139 sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */
140 sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */
141 /* remap CS0 (SRAM) */
142 pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
143
144 /* configure CS1 (ST16552 / CHAN A) */
145 sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */
146 sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */
147 sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */
148 sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */
149 /* remap CS1 (ST16552 / CHAN A) */
150 /* remap CS1 (ST16552 / CHAN A) */
151 pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
152
153 /* configure CS2 (ST16552 / CHAN B) */
154 sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */
155 sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */
156 sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */
157 sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */
158 /* remap CS2 (ST16552 / CHAN B) */
159 pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
160
161 /* configure CS3 (BCSR) */
162 sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */
163 sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */
164 sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */
165 sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */
166 /* remap CS3 (DISPLAY and BCSR) */
167 pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
168 }
169
170 void sysOutLong(ulong address, ulong value)
171 {
172 *(ulong*)address = cpu_to_le32(value);
173 }
174
