VIVADO(4)

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以欢喜心过生活

以平常心生情味

以柔软心除挂碍                                     --------------林清玄《人间有味是清欢》

Synthesis :

 

 

 -flatten_hierarchy:

     -none: this option instructs the synthesis tool to never flatten the hierarchy, the output of synthesis will have the exact same hierarchy as the originaln RTL (不会优化边界，也同时保留原本的RTL层次)

     -full ： this option instructs the tool to fully flatten the hierarchy leaving only the top level (完全展开设计，不会保留RTL层次)

     -rebuilt ： this is the default flatten_hierarchy option , rebuilt allows the synthesis tool to flatten the hierarchy , perform synthesis , and then rebuild the hierarchy based on the original RTL , this value allows the QoR benefit of cross-boundry optimizations, with a final hierarchy that is similar to the RTL for ease of analysis (缺省：综合时打平设计，可以优化边界，综合后的网表可以从新建立RTL层次（相似）)

-no_lc （lc：LUT Combining）

     -no_lc unchecked:     (same input)

 

 

 

 Pro : saves area   (节约资源)

 

Con ：could induce congestion  ( 引起布线拥塞)

 

      -no_lc checked :           (same input)               

 

 Guideline: if >15% of LUT use both O5 and O6 then     -on_lc checked   

tips:     use report_utilization and look for LUTs with O5 and O6 after implementation 

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SRL：basic ports ：

  Q、D、CLK、CE、A   

tips : do not support reset

XILINX：

SRL16E、SRL32E

tips:SRL16:

 

 

 tips: SRL32E:

 

 

 

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- stl_style

  -srl_reg:

   

 

 

   -reg_srl :

   

 

   -reg_srl_reg ：

 

 

   - register ：

   

 

   -srl ：

 

 

  tips: Make sure  -sherg_min_size is reasonable 

SRL: 

  advantages : less area 、Performance (Routing delays between cascaded ffs decreases the performance comparing to SRL )

Tips : the clock-to-output time of a flop is much lower than clock-to-output of an SRL that's why is mah=kes sense to add a flop on the output of an SRL .

  -srl:                                                    -srl_reg :

                                 

 

 

   -ram_style/rom_style

   instructs the Vivado synthesis tool on how to infer memory

   -block:    

  -distributed:   LUT RAMs

 

 

   use_dsp48

  -Mult

  - Mult-add & Mult-sub

  - Mult-accumulate

   --------------------------------

  addres、 subtracters、and accumulators are implemented with the fabric instead of with 48 blocks by default

(当使用的资源过多时，也可以声明使用 use_dsp48 来减少使用的资源)

block_box   （字面意思  黑盒子）

 it can turn a whole level of hierarchy off and enable synthesis to create black box for that module or entity . 

 

 

 

dont_touch   （防止综合优化掉期望的信号）

use the DONT_TOUCH attribute in place of KEEP 。

unlike KEEP , DONT_TOUCH is forward -annotated to place and route to prevent logic optimization.

fsm_enconding

(提供状态机编码方式)

 

 

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Create Multiple Runs

   

 

 

 each run can have different constraint、different part and different strategy