AXI-4 总结-introduction

AXI还是比较牛逼的，靠着ARM的广泛应用，AXI也成了重要标准协议。
最近公司也从自有协议开始往AXI上面转，因此新人培训也加入了AXI的内容。

今天看完了ARM的introduction文档，做个简单的小总结，还有一些不明白的地方记录下来。
顺便吐槽一下，为了政治正确，现在Master和Slave都改名叫Manager和Subordinate了，无语。

Diversity and inclusion are important values to Arm. Because of this, we are re-evaluating the terminology we use in our documentation. Older Arm documentation, including the AMBA AXI and ACE protocol specification, uses the terms master and slave. This guide uses replacement terminology, as follows:
• The new term manager is synonymous with master in older documentation.
• The new term subordinate is synonymous with slave in older documentation.

因为培训的昨夜里不要求实现AXI的全部功能，而且培训用的是AXI3的标准（估计用的也是很老的ARM ip...），所以这里也跳过了文档的一部分章节。我倒，我说我怎么看这么快呢。

Atomic access部分跳过，AXI4的特有功能例如tuser部分跳过。

对于任意的BUS，有两个最重要的指标：Bandwidth和Latency。
Bandwidth = BUS bit width * BUS frequency.
Latency = the time for the completion of the first transfer.

这里顺便说一下transfer和transaction的区别。
transfer对应1T，transaction是对应一次传输操作，或者说一个传输包。
通常一个transaction由一个或者多个transfer组成。

• A transfer is a single exchange of information, with one VALID and READY handshake.
• A transaction is an entire burst of transfers, containing an address transfer, one or more data transfers, and, for write sequences, a response transfer.

AXI作为AMBA的一部分，随着AMBA的演进而被提出。在演进过程中，有些经典的协议并没有被抛弃。
其典型代表就是AHB和APB：

AHB is pipelined for performance, while APB is not pipelined for design
simplicity.
APB是严格的两步操作，指令和数据分布在两个连续的周期之内。

AXI支持Exclusive access，多个M可以同时访问一个S，这里面涉及类似访问锁的机制，可以实现独占。并且还可以对

AXI支持权限控制，这部分和ARM自带的安全控制逻辑有关。

AXI支持Multi issue，即便之前的transaction没有完成，依然可以继续发command。

地址和数据操作之间的时序要求不严格，并不是说没有要求，具体要求总结如下：

WLAST transfer must complete before BVALID is asserted.
This dependency does not exist in AXI3 but is introduced for AXI4:
In AXI3, the address does not have to be seen before a write response is sent.
In AXI4, all of the data and the address must have been transferred before the manager can see a write response

读地址没发完之前不能发读数据。

RVALID cannot be asserted until ARADDR has been transferred.

写地址没发完可以发写数据。

WVALID can assert before AWVALID.

支持非对齐的数据传输。
其数据传输分为三种模式：Fixed，Incremental，Wrap。
Fix只有一个地址，对应FIFO操作。

Incremental的地址可以是unaligned。地址顺序递增。

WRAP模式通常用作Cache line的传输，当地址递增到达对应cache line的上限之后，地址循环回到低位地址。

The AXI protocol is a point-to-point specification, not a bus specification. Therefore, it describes only the signals and timing between interfaces.

AXI分为5路：AW，W，B，AR，R。分别是写指令，写数据，写回复，读指令，读数据。
读也有读回复，但是和读数据放到了一起：

However, there is no need for a Read Response channel, because a read response is passed as part of the Read Data channel.

读与写之间没有时序关系：

There is no timing relationship between the groups of read and write channels. This means that a read sequence can happen at the same time as a write sequence.

支持非对齐的数据传输。

支持第一次transfer unaligned，后续aligned：

The AXI protocol supports transactions with an unaligned start address that only affects the first transfer in a transaction. After the first transfer in a transaction, all other transfers are aligned.

支持乱序传输。

支持burst模式。

之前项目用的是AXI-Stream，对这个握手还是了解的。
握手的机制也比较简单，主要的一个坑就是避免死锁的机制，M端的ready不能等S端的valid，反过来可以。这个在做AXI接口的时候要注意。

• A source cannot wait for READY to be asserted before asserting VALID.
• A destination can wait for VALID to be asserted before asserting READY.

多周期的数据写入时，既可以用last信号，也可以数周期。

The manager drives the WLAST high to indicate the final WDATA. This means that the
subordinate can either count the data transfers or just monitor WLAST.

BRESP一次transaction只发一个，即便写入过程中出现错误，也必须等待写入结束之后再回复BRESP。

Once all WDATA transfers are received, the subordinate gives a single BRESP value on the B channel. One single BRESP covers the entire burst. If the subordinate decides that any of the transfers contain an error, it must wait until the entire burst has completed before it informs the manager that an error occurred.

RRESP与BRESP不同，RRESP对应transfer。

One difference between a read transaction and a write transaction is that for a read transaction there is an RRESP response for every transfer in the transaction. This is because, in the write transaction, the subordinate has to send the response as a separate transfer on the B channel. In the read transaction, the subordinate uses the same channel to send the data back to the manager and to indicate the status of the read operation.

AXI3的AWLEN是4bit，AXI4是8bit，这个对应"the length of the transaction in the number of transfers"。其他区别一并总结如下：

写通道：

• For the write address channel, the AWLEN signal is wider for the AXI4 protocol. Therefore, AXI4 is able to generate longer bursts than AXI3.
• AXI4 reduces the AWLOCK signal to a single bit to only accommodate exclusive transfers because locked transfers are not supported.
• AXI4 adds the AWQOS signal to the AW channel. This signal supports the concept of quality of service (QoS) in the AXI4 protocol.
• AXI4 adds the AWREGION signal to the AW channel. This signal supports subordinate
regions which allow for multiple logical interfaces from a single physical subordinate interface.
• AXI4 removes the WID signal from the W channel. This is because write data reordering is no longer allowed.
• AXI4 adds user-defined signals to each channel.

读通道：

• For the AXI4 protocol, the read address length signal ARLEN is wider. Therefore, AXI4 is able to generate longer read bursts than AXI3.
• AXI4 reduces the ARLOCK signal to a single bit to only accommodate exclusive transfers because locked transfers are not supported.
• As with the write channel signals, the concepts of quality of service and subordinate regions apply to read transactions. These use the ARQOS and ARREGION signals in the AR channel.
• AXI4 adds user-defined signals to the two read channels.

AXI4不支持locked transactions，AXI3必须支持。

AxSize,3bit,对应每次transfer的byte数量，分别是1，2，4，...，128。

write data strobe，这个是M告诉S这次transfer中，哪几个byte是有效的。

Using this method, write transactions can be early terminated by setting the remaining transfer byte lane strobes to 0, although the remaining transfers must still be completed. The WSTRB signal can also change between transfers in a transaction.

transaction ID，有了ID之后就可以实现乱序传输。
ID对应transaction，也就是说，同一个transaction之内的transfer的ID相同。

乱序传输并非完全乱序，同样有一些ordering rules:

写数据的顺序要和写指令相同。

Write data on the W channel must follow the same order as the address transfers on the AW channel.

BRESP可以是任意顺序。

Transactions with different IDs can complete in any order.

同一个ID的不同transaction必须按照指令发送顺序完成。

A manager can have multiple outstanding transactions with the same ID, but they must be performed in order and complete in order.

For transactions with the same ID, read data on the R channel must be returned in the order that they were requested.

不同ID的读数据可以是任意顺序回复，并且可以交错混合发送。

Read data for different IDs on the R channel has no ordering restrictions. This means that the subordinate can send it in any order.

The read data for the different IDs on the R channel can be interleaved, with the RID value differentiating which transaction the data relates to.

公司的自有协议改自MIPS，没有把读写指令通道分开。