C2verilog_leixin

 

module loop(
            input clk,
            input rst_n,
            input [7:0]check_sum,
            output [7:0]check_sum_o
            );
    integer i;
    reg [7:0]ccc;
    always@(posedge clk or negedge rst_n)   
        if(!rst_n)
            check_sum_o<='d0;
        else begin
            ccc=check_sum;
            for(i=0;i<8;i=i+1)begin
                ccc={ccc[6:0],1'b0}^{{8{ccc[7]}}&8'h31};
            end
            check_sum_o=ccc;
        end
endmodule

https://zhuanlan.zhihu.com/p/69969288