（VHDL小程序003）用VHDL设计寄存器

该寄存器在clk上升沿并且ctrl为1时，寄存并输出数据到pout。

code如下：

entity reg is

     port(

          indata:in bit_vector;

          clk:in bit;

          ctrl:in bit;

          pout:out bit_vector

          );

end reg;

 

architecture func of reg is

begin

     process

     begin

          wait until clk'event and clk='1';

          if(ctrl='1') then pout<=indata;

          end if;

     end process;

end func;

====================================

一个移位寄存器，当线选信号i的高三位为000时，输出q为输入f的数据；当i高三位为100时，q右移1位，高位为q3；当i高三位为110时，q左移1位，低位为q0；其他情况，q不变。

code如下：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

 

entity reg is

     port(

          f:in std_logic_vector(3 downto 0);

          clk:in std_logic;

          i:in std_logic_vector(8 downto 0);

          q0,q3:in std_logic;

          q:inout std_logic_vector(3 downto 0)

          );

end reg;

 

architecture func of reg is

begin

     aaa:block(not clk'stable and clk='1')

     begin

          q<=guarded f when i(8 downto 6) ="000" else

               q3&q(3 downto 1) when i(8 downto 6)="100" else

               q(2 downto 0)&q0 when i(8 downto 6)="110" else     --std_logic 必须列全，故最后的else必须加上。               

               q;

     end block aaa;                                                                  --block必须加标识符，不然，编译不通过。

end func;