（VHDL小程序000）用VHDL设计有无控制端的加减乘除法运算器

带有控制端的code：

entity adder is

     port(in1:in bit_vector;

          in2:in bit_vector;

          ctrl:in bit;

          pout:out bit_vector

          );

end adder;

 

architecture func of adder is

begin

     process(ctrl)

     begin

          if(ctrl='1') then pout<=in1+in2;--将“＋”变为“－”“*”“/”，变为其他运算器

          end if;

     end process;

end func;

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无控制端的code：

entity adder is

     port(in1:in bit_vector;

          in2:in bit_vector;

          pout:out bit_vector;

          );

end entity;

 

architecture func of adder is

begin

     process(in1,in2)

     begin

          pout<=in1+in2;--将“＋”变为“－”“*”“/”，变为其他运算器

     end process;

end architecture;