Hello World! 但是FPGA
module helloworld(clock,en,char0[0:6],char1[0:6],char2[0:6],char3[0:6],char4[0:6],char5[0:6]); input clock; input en; output reg [0:6]char0; output reg [0:6]char1; output reg [0:6]char2; output reg [0:6]char3; output reg [0:6]char4; output reg [0:6]char5; initial begin char0[0:6]=7'b1111111; char1[0:6]=7'b1111111; char2[0:6]=7'b1111111; char3[0:6]=7'b1111111; char4[0:6]=7'b1111111; char5[0:6]=7'b1111111; end always@(posedge clock) begin case(en) 1'b0:begin char5[0:6]=7'b1001000; char4[0:6]=7'b0110000; char3[0:6]=7'b1110001; char2[0:6]=7'b1110001; char1[0:6]=7'b0000001; char0[0:6]=7'b1111111; end default:begin char5[0:6]=7'b1101101; char4[0:6]=7'b1011011; char3[0:6]=7'b0000001; char2[0:6]=7'b0001000; char1[0:6]=7'b1110001; char0[0:6]=7'b0000001; end endcase end endmodule
非常抽象的WORLD
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