时序约束小笔记（一）

0.多看UG953,949，903

1.进入PLL/MMCM/PHASER的信号不需要做约束；

2.管脚上进来的时钟要做主时钟约束，出去的信号要做衍生时钟约束；Recommended: Define all primary clocks first. They are needed for defining the generated clocks.

2.1主时钟的定义位置问题：需要参考特权同学的书籍；

Important: The Vivado IDE ignores all clock tree delays coming from cells located upstream from the point at which the primary clock is defined. 
If you define a primary clock on a pin in the middle of the design, only part of its latency is used for timing analysis. 
This can be a problem if this clock communicates with other related clocks in the design, 
because the skew, and consequently the slack, value between the clocks can be inaccurate.

3.对于进来的信号通过时钟做inputdelay约束，出去的信号做outputdelay约束；

4.IP内部的时序违例是难以处理的，但是通过改变优化策略一般能得到解决；

5.打拍和逻辑分割是降低逻辑延时的有效手段；

6.跨时钟域信号需要setfalse或set异步时钟group；

7.case不要太深，也不要嵌套太多case；

8.if类语句条件尽可能不涉及位宽太大的数，会引起skew；

9.灵活插入寄存器；