STM32F4xx usb库源码详解：HAL_PCDEx_SetRxFiFo 和 HAL_PCDEx_SetTxFiFo

HAL_PCDEx_SetRxFiFo 和 HAL_PCDEx_SetTxFiFo

这两个函数的作用是：该EndPoint数据传输最大数量的限定

除前面贴子里廛的影响数据传输量的函数外，这两个HAL_PCDEx_SetRxFiFo / HAL_PCDEx_SetTxFiFo函数也值得注意。

其一，这两个函数是有使用顺序的（参考USBD_LL_Init函数）：HAL_PCDEx_SetRxFiFo先设置GRXFSIZ，然后HAL_PCDEx_SetTxFiFo中会用到这个GRXFSIZ。

另外，所有EP共享的Rx FIFO + 所有的Tx FIFO，最大允许在RAM中开辟的空间为1.25kB（i.e. max. 0x140 words）

下面的代码中，Tx_Offset是指bit0~15，存放的是地址偏移量。"<<16"是指bit16~31，存放是当前EndPoint的FIFO的大小。

/**
  * @brief  Set Tx FIFO
  * @param  hpcd PCD handle
  * @param  fifo The number of Tx fifo
  * @param  size Fifo size
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
  uint8_t i = 0;
  uint32_t Tx_Offset = 0U;
​
  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
      When a TxFIFO is not used, the Configuration should be as follows: 
          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
         --> Txm can use the space allocated for Txn.
         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
         --> Txn should be configured with the minimum space of 16 words
     The FIFO is used optimally when used TxFIFOs are allocated in the top 
         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
  
    //the RAM size that must be allocated to the RxFIFO.
    Tx_Offset = hpcd->Instance->GRXFSIZ;
  
    /*
    DIEPTXF0_HNPTXFSIZ <=equivalent to DIEPTXF0=>
    DEVICE MODE:
    Bits 31:16 TX0FD: Endpoint 0 TxFIFO depth
        This value is in terms of 32-bit words.
        Minimum value is 16 Maximum value is 256
    Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address
        This field contains the memory start address for the endpoint 0 transmit FIFO RAM
        
    DIEPTXFx
    Bits 31:16 INEPTXFD: IN endpoint TxFIFO depth
        This value is in terms of 32-bit words.
        Minimum value is 16 
        The power-on reset value of this register is specified as the largest IN endpoint FIFO number depth.
    
    Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address
        This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 
    */
  if(fifo == 0){      
    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
  }
  else
  {
    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
    for (i = 0; i < (fifo - 1); i++)
    {
      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U);
    }
    
    /* Multiply Tx_Size by 2 to get higher performance */
    hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);        
  }
  
  return HAL_OK;
}