输入：singal、clk、_clr、8bit count
输出：dout
当_clr low 时 dout 输出 为low
当_clr hi 时 clk 升沿采样,连续count 个singal 为hi 时dout输出为hi
否则 dout 输出为low
代码1：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Entity Declaration
ENTITY countup1 IS
PORT
(
singal,clk,n_rst : IN STD_LOGIC;
countset : IN STD_LOGIC_VECTOR(7 downto 0);
sinout : OUT STD_LOGIC
);
END countup1;
-- Architecture Body
ARCHITECTURE a_architecture OF countup1 IS
begin
process(n_rst,clk)
VARIABLE count : std_logic_vector(7 downto 0);
begin
if n_rst = '0' then
count := "00000000" ;
else
if rising_edge(clk) then
if singal = '1' then
count := count + 1 ;
if count > 254 then
count := "11111100";
end if ;
else
count := "00000000" ;
end if ;
end if ;
end if ;
if count > countset then
sinout <= '1' ;
else
sinout <= '0' ;
end if ;
end process;
END a_architecture;
RTL Viewer：
资源用量：
代码2：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Entity Declaration
ENTITY countup2 IS
PORT
(
singal,clk,n_rst : IN STD_LOGIC;
countset : IN STD_LOGIC_VECTOR(7 downto 0);
sinout : OUT STD_LOGIC
);
END countup2;
-- Architecture Body
ARCHITECTURE a_architecture OF countup2 IS
begin
process(n_rst,clk)
VARIABLE count : std_logic_vector(7 downto 0);
begin
if n_rst = '0' then
count := countset ;
else
if rising_edge(clk) then
if singal = '1' then
if count = 0 then
sinout <= '1' ;
else
count := count - 1 ;
sinout <= '0' ;
end if ;
else
count := countset ;
sinout <= '0' ;
end if ;
end if ;
end if ;
end process;
END a_architecture;
RTL Viewer：
资源用量：
代码3：
module sample(
input signal,
input clk,
input clr_n,
input[7:0] count,
output reg dout);
reg[7:0] cnt;
always@(posedge clk or negedge clr_n)
begin
if(!clr_n) begin cnt <= 1'b0; dout <= 1'b0; end
else begin
if(signal)
begin
if((cnt<count) && !dout) begin cnt <= cnt + 1'b1; dout <= 1'b0; end
else begin cnt <= 1'b0; dout <= 1'b1; end
end
else begin cnt <= 1'b0; dout <= 1'b0; end
end
end
endmodule
RTL Viewer：
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比一比三个代码，哪个好些？
