错误记录：[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair.

报错详情

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[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.
instance_name/inst/clkin1_ibuf/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X1Y101
instance_name/inst/mmcme3_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X1Y1

The above error could possibly be related to other connected instances. Following is a list of 
all the related clock rules and their respective instances.

Clock Rule: rule_mmcm_bufg
Status: PASS 
Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
BUFG
instance_name/inst/mmcme3_adv_inst (MMCME3_ADV.CLKOUT1) is provisionally placed by clockplacer on MMCME3_ADV_X1Y1
instance_name/inst/clkout2_buf (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X1Y47

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS 
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
instance_name/inst/clkout2_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X1Y47

解释

全局时钟功能的IO引脚和MMCM对放置不佳

解决方法

在usr_clk进入clk_wiz_0 IP核之前添加一个 BUFG。

点击查看代码

module ex_module (
    input usr_clk,
    output wire clk_out1,
    output wire clk_out2,
    output wire clk_out3
);

    wire usr_clk_bufg; // 新增 BUFG 的输出信号

    BUFG usr_clk_bufg_inst (.I(usr_clk), .O(usr_clk_bufg)); // 插入 BUFG

    clk_wiz_0 instance_name
       (
        // Clock out ports
        .clk_out1(clk_out1),     // output clk_out1 5Mhz
        .clk_out2(clk_out2),     // output clk_out2 10Mhz
        .clk_out3(clk_out3),     // output clk_out3 50Mhz
       // Clock in ports
        .clk_in1(usr_clk_bufg)      // input clk_in1, 连接到 BUFG 的输出
    );

endmodule