错误记录：Poor placement for routing between an IO pin and BUFG.

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14.错误记录：Poor placement for routing between an IO pin and BUFG.01-03

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错误代码

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[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SCL_IBUF] >
 
TEXT
Clock Rule: rule_gclkio_bufg
Status: FAILED
Rule Description: An IOB driving a BUFG must use a CCIO in the same half side (top/bottom) of chip as the BUFG
 
SCL_IBUF_inst (IBUF.O) is locked to IOB_X0Y91
SCL_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

# 环境 Vivado 2023.2 IIC的从机代码，SCL线出现了问题。

错误分析

如果将 GPIO 用作时钟输入，通常需要一个 IBUF（输入缓冲器）和一个 BUFG（全局缓冲器）的级联，此时的bufg没有和ibuf处在一个时钟域（GCIO全局时钟资源），现在只能将scl_ibuf信号错误降为警告，相当于牺牲了信号质量

如何解决

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SCL_IBUF]