Vivado联合Modelsim仿真

合集 - 学习(18)

1.VSCode环境配置（QT）2024-08-012.Log4cplus导入QT5（VSCode）2024-08-013.不显示命令提示符窗口（CMake）2024-08-274.LVDS（FPGA）2024-09-085.更新QT Creator 14后launch debugger报错2024-09-196.VSCode配置Python（记录）2024-10-097.QT打包exe（含错误解决方法）2024-10-16

8.Vivado联合Modelsim仿真2024-10-16

9.C++静态变量2024-10-1910.解决Vivado连接不到硬件的报错2024-11-0711.vivado系统任务学习2024-11-2212.QT打开一直转圈2024-12-0313.QT导入Eigen库2024-12-0314.错误记录：Poor placement for routing between an IO pin and BUFG.01-0315.错误记录：[Synth 8-6895] The reference checkpoint01-0516.VSCode中CMake tools插件配置文件01-0817.QT添加外部库（CMake Mingw）01-0918.错误记录：[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair.03-03

收起

版本

vivado2023.2
modelsim10.6d

报错信息

WARNING: [Vivado 12-5495] Detected incompatible modelsim simulator installation version '10.6d'! The supported simulator version for the current Vivado release is '2023.2'
我这里没有管warning，发现实际是能用的

编译仿真库

点击菜单栏Tools-->Compile Simulation Libaries

Compiled library location选择你想要保存的库目录
GCC选择vivado目录下的编译器（供参考：D:\Software\Vivado2023.2\Vivado\2023.2\tps\mingw\8.3.0\win64.o\nt\bin）

报错

点击查看代码

*---------------------------------------------------------------------------------------------------------------------*
*  xdfe_nr_prach_v2_0_1                   | verilog  | xdfe_nr_prach_v2_0_1                   | 0        | 24         *
*---------------------------------------------------------------------------------------------------------------------*
*  xdfe_ofdm_v2_0_0                       | vhdl     | xdfe_ofdm_v2_0_0                       | 0        | 0          *
*---------------------------------------------------------------------------------------------------------------------*
*  xdfe_ofdm_v2_0_0                       | verilog  | xdfe_ofdm_v2_0_0                       | 0        | 92         *
*---------------------------------------------------------------------------------------------------------------------*
*  xsdbs_v1_0_3                           | verilog  | xsdbs_v1_0_3                           | 0        | 0          *
*---------------------------------------------------------------------------------------------------------------------*
*  zynq_ultra_ps_e_vip_v1_0_15            | verilog  | zynq_ultra_ps_e_vip_v1_0_15            | 0        | 0          *
*---------------------------------------------------------------------------------------------------------------------*
 
ERROR: [Vivado 12-23674] compile_simlib failed to compile for modelsim with error in 1 library (cxl_error.log, Number of error(s) = 1)
INFO: [Vivado 12-7167] Writing compiled library information...
INFO: [Vivado 12-7165] Finished writing compiled library information.
compile_simlib: Time (s): cpu = 00:01:41 ; elapsed = 00:50:23 . Memory (MB): peak = 1784.445 ; gain = 76.781
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.

编译的结果，省略了部分
暂时没有解决这个报错

点击查看代码

*  ldpc_5gnr_lite_v1_0_1                  | verilog  | ldpc_5gnr_lite_v1_0_1                  | 1        | 158        *

主要错误就是这个库编译错误；未解决

实际运行

1. 设置Modelsim的安装路径（这个地址看个人电脑）；
2. 设置GCC的安装路径（这个也可以改成自己的mingw版本，默认的话依照前面编译库的时候涉资的路径）；
3. 设置仿真库的路径，这个是之前编译时设置的地址。

Setting中设置仿真器为ModelSim

检查编译仿真库的路径是否是之前的编译的地址
（启用增量编译可能会报错，如果启用可以加速）