LVDS（FPGA）

合集 - 学习(18)

1.VSCode环境配置（QT）2024-08-012.Log4cplus导入QT5（VSCode）2024-08-013.不显示命令提示符窗口（CMake）2024-08-27

4.LVDS（FPGA）2024-09-08

5.更新QT Creator 14后launch debugger报错2024-09-196.VSCode配置Python（记录）2024-10-097.QT打包exe（含错误解决方法）2024-10-168.Vivado联合Modelsim仿真2024-10-169.C++静态变量2024-10-1910.解决Vivado连接不到硬件的报错2024-11-0711.vivado系统任务学习2024-11-2212.QT打开一直转圈2024-12-0313.QT导入Eigen库2024-12-0314.错误记录：Poor placement for routing between an IO pin and BUFG.01-0315.错误记录：[Synth 8-6895] The reference checkpoint01-0516.VSCode中CMake tools插件配置文件01-0817.QT添加外部库（CMake Mingw）01-0918.错误记录：[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair.03-03

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差分输入时钟缓冲器（IBUFDS）

点击查看代码

 // IBUFDS: Differential Input Buffer
 //         7 Series
 // Xilinx HDL Language Template, version 2024.1
 IBUFDS #(
   .DIFF_TERM("FALSE"),       // Differential Termination
   .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE"
   .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
 ) IBUFDS_inst (
   .O(O),  // Buffer output
   .I(I),  // Diff_p buffer input (connect directly to top-level port)
   .IB(IB) // Diff_n buffer input (connect directly to top-level port)
 );
 // End of IBUFDS_inst instantiation

差分输出时钟缓冲器（OBUFDS）

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// OBUFDS: Differential Output Buffer
 //         7 Series
 // Xilinx HDL Language Template, version 2024.1
 OBUFDS #(
   .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
   .SLEW("SLOW")           // Specify the output slew rate
 ) OBUFDS_inst (
   .O(O),     // Diff_p output (connect directly to top-level port)
   .OB(OB),   // Diff_n output (connect directly to top-level port)
   .I(I)      // Buffer input
 );
 // End of OBUFDS_inst instantiation

三态差分输入输出（IOBUFDS）

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// IOBUFDS: Differential Bi-directional Buffer
 //          7 Series
 // Xilinx HDL Language Template, version 2024.1
 IOBUFDS #(
   .DIFF_TERM("FALSE"),     // Differential Termination ("TRUE"/"FALSE")
   .IBUF_LOW_PWR("TRUE"),   // Low Power - "TRUE", High Performance = "FALSE"
   .IOSTANDARD("BLVDS_25"), // Specify the I/O standard
   .SLEW("SLOW")            // Specify the output slew rate
 ) IOBUFDS_inst (
   .O(O),     // Buffer output
   .IO(IO),   // Diff_p inout (connect directly to top-level port)
   .IOB(IOB), // Diff_n inout (connect directly to top-level port)
   .I(I),     // Buffer input
   .T(T)      // 3-state enable input, high=input, low=output
 );
 // End of IOBUFDS_inst instantiation

以下是我使用的118评估版的IO

补充电平特性

参考

7 Series FPGAs SelectIO Resources User Guide (UG471)
7 Series FPGA and Zynq 7000 SoC Libraries Guide（ug953）
Zynq UltraScale+ RFSoC Data Sheet:DC and AC Switching Characteristics(DS926)