随笔分类 -  FPGA

摘要:报错详情 点击查看代码 [Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG 阅读全文
posted @ 2025-03-03 22:10 Little_R 阅读(2) 评论(0) 推荐(0) 编辑
摘要:报错详情 点击查看代码 [Synth 8-6895] The reference checkpoint E:/Projects/Vivado2023/2.ExampleDesign_my/iic_ms/iic_ms.srcs/utils_1/imports/synth_1/Master.dcp is 阅读全文
posted @ 2025-01-05 16:59 Little_R 阅读(92) 评论(0) 推荐(0) 编辑
摘要:错误代码 点击查看代码 [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may 阅读全文
posted @ 2025-01-03 00:43 Little_R 阅读(27) 评论(0) 推荐(0) 编辑
摘要:命令 $readmemh(十六进制)读取16进制的数据 $readmemb(二进制)读取2进制的数据 文件路径位置 相对路径 要放在这里 绝对路径 也可以绝对路径的方式使用 阅读全文
posted @ 2024-11-22 18:38 Little_R 阅读(35) 评论(0) 推荐(0) 编辑
摘要:报错 ERROR: [Common 17-39] 'connect_hw_server' failed due to earlier errors. 报错详细信息 点击查看代码 connect_hw_server -allow_non_jtag INFO: [Labtools 27-2285] Co 阅读全文
posted @ 2024-11-07 16:05 Little_R 阅读(551) 评论(0) 推荐(0) 编辑
摘要:版本 vivado2023.2 modelsim10.6d 报错信息 WARNING: [Vivado 12-5495] Detected incompatible modelsim simulator installation version '10.6d'! The supported simu 阅读全文
posted @ 2024-10-16 17:09 Little_R 阅读(224) 评论(0) 推荐(0) 编辑

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