HDLBits_6.25

1|04.验证：读取模拟

1|14.1查找代码中的错误

4.1.1 多用复路器（2_1_Mux）

//Wrong
module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output out  );

    assign out = (~sel & a) | (sel & b);

endmodule

//Right:out位宽不对，表达式不对
module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out);

    assign out = sel ? a : b;

endmodule

 

4.1.2 用5与非实现3与非（NAND）

//Wrong
module top_module (input a, input b, input c, output out);//

    andgate inst1 ( a, b, c, out );

endmodule

//Right:输入输出的对应关系不对，且参数数量也不对
module top_module (input a, input b, input c, output out);//
    
	wire and_out;
    
    andgate inst1 ( and_out, a, b, c, 1, 1);
    
    assign out = ~and_out;

endmodule

  

4.1.3 四路选择器（8bit_4_1_Mux）

//Wrong
module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire mux0, mux1;
    mux2 mux0 ( sel[0],    a,    b, mux0 );
    mux2 mux1 ( sel[1],    c,    d, mux1 );
    mux2 mux2 ( sel[1], mux0, mux1,  out );

endmodule

//Right:sel[1]区分不了c和d，此处应该还是sel[0]。此外例化名与变量名不能重复；且wire信号的位宽也不对
module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire [7:0] mux00, mux11;
    mux2 mux0 ( sel[0],    a,    b, mux00 );
    mux2 mux1 ( sel[0],    c,    d, mux11 );
    mux2 mux2 ( sel[1], mux00, mux11,  out );

endmodule

 

4.1.4 Add/Sub

//Wrong:
// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (~out)
            result_is_zero = 1;
    end

endmodule

//Right:因为result_is_zero为reg型，当其为1后一直为1，因为没有其他状态能使其改变，且需锁存状态，因为if未遍历所有状态
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (out == 8'd0) begin
            result_is_zero = 1;
        end
        else begin
            result_is_zero = 0;
        end
    end

endmodule

 

4.1.5 case statement

//Wrong
module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid=1 );//

     always @(*)
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'd26: out = 3;
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            6'h46: out = 9;
            default: valid = 0;
        endcase

endmodule

//Right:默认输出valid=1不能按上图所示的编写代码，默认的输入可以；其次进制8'd26需改成8进制
module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid);

     always @(*) begin
         case (code)
            8'h45: out = 4'd0;
            8'h16: out = 4'd1;
            8'h1e: out = 4'd2;
            8'h26: out = 4'd3;
            8'h25: out = 4'd4;
            8'h2e: out = 4'd5;
            8'h36: out = 4'd6;
            8'h3d: out = 4'd7;
            8'h3e: out = 4'd8;
            8'h46: out = 4'd9;
            default: begin
                out = 4'd0;
            end
        endcase

         if(out == 4'd0 && code!= 8'h45) begin
            valid = 1'b0;
        end
        else begin
            valid = 1'b1;
        end
     end
     		              
endmodule

 

__EOF__

本文作者：LhTian
本文链接：https://www.cnblogs.com/LhTian/p/17502476.html
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