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zedboard基于vivado的试验
试验①：点亮一个led灯,使用一个按钮做复位。
project_2.v
module project_2(
input clk, //时钟输入
input rst, //复位，高电平有效
output reg led //led输出
);
always@(posedge clk or posedge rst)begin
if(rst) //复位按钮按下就给led一个低电平
led<=1'b0;
else //否则给一个高电平
led<=1'b1;
end
endmodule
生成的schematic图像
手动添加管脚约束：
时钟引脚：Y9
led灯引脚：T22
复位rst引脚: P16
生成的project_2.xdc文件：
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property PACKAGE_PIN T22 [get_ports led]
set_property PACKAGE_PIN P16 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
经过生成比特流之后，链接板子进行写入。
2024年3月13日15:40:52
F22红灯点亮（注意将串联的开关处于打开状态）
按下按键P16，程序复位。
试验②：流水灯
project_3.v
module project_3(
input clock,//100M
input reset,//SW0
output [7:0] led//LED0~LED7
);
reg [32:0] count;
reg [2:0] led_cnt;
reg [7:0] led_reg;
//0.5s计数
always@(posedge clock or negedge reset)begin
if(!reset)
count <= 32'd0;
else if(count == 32'd50000000 - 1'b1)
count <= 32'd0;
else
count <= count + 1'b1;
end
//led计数0~7
always@(posedge clock or negedge reset)begin
if(!reset)
led_cnt <= 3'd0;
else if(count == 32'd50000000 - 1'b1)
led_cnt <= led_cnt + 1'b1;
else
led_cnt <= led_cnt;
end
//根据计数值点亮led
always@(posedge clock or negedge reset)begin
if(!reset)
led_reg <= 8'b00000000;
else case(led_cnt)
0: led_reg <= 8'b00000001;
1: led_reg <= 8'b00000010;
2: led_reg <= 8'b00000100;
3: led_reg <= 8'b00001000;
4: led_reg <= 8'b00010000;
5: led_reg <= 8'b00100000;
6: led_reg <= 8'b01000000;
7: led_reg <= 8'b10000000;
default:led_reg <= 8'b00000000;
endcase
end
assign led = led_reg;
endmodule
生成的schematic图像
手动添加管脚约束：
