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Parameterized true dual-port RAM megafunction. The altsyncram megafunction is available for Cyclone™, Stratix™, and Stratix™ GX devices only.
Altera® recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager (Tools menu).
This topic contains the following information:
- AHDL Function Prototype (also applies to Verilog HDL)
- VHDL Component Declaration
- VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
- Port Descriptions
- Parameter Descriptions
AHDL Function Prototype (port name and order also apply to Verilog HDL):
FUNCTION altsyncram (
wren_a, wren_b, data_a[OPERATION_MODE != "ROM" ? WIDTH_A - 1 : 0..0], data_b[(OPERATION_MODE == "BIDIR_DUAL_PORT") ?
WIDTH_B - 1 : 0..0], address_a[WIDTHAD_A - 1..0], address_b[(OPERATION_MODE == "BIDIR_DUAL_PORT" # OPERATION_MODE== "DUAL_PORT") ?
WIDTHAD_B - 1 : 0..0], clock0, clock1, clocken0, clocken1, rden_b, aclr0, aclr1, byteena_a[OPERATION_MODE != "ROM" ?
((WIDTH_A > 15) ? ((WIDTH_BYTEENA_A > 1 ? WIDTH_BYTEENA_A-1 : 0)) : 0 ): 0..0], byteena_b[OPERATION_MODE == "BIDIR_DUAL_PORT" ? ((WIDTH_B > 15)?
(WIDTH_BYTEENA_B > 1 ? WIDTH_BYTEENA_B-1 : 0) : 0 ): 0..0] )
WITH ( OPERATION_MODE, WIDTH_A, WIDTHAD_A, NUMWORDS_A, INDATA_ACLR_A, WRCONTROL_ACLR_A, ADDRESS_ACLR_A, WIDTH_B, WIDTHAD_B, NUMWORDS_B, INDATA_REG_B, INDATA_ACLR_B,
WRCONTROL_WRADDRESS_REG_B, WRCONTROL_ACLR_B, ADDRESS_ACLR_B, OUTDATA_REG_A, OUTDATA_ACLR_A, BYTEENA_ACLR_A, RDCONTROL_REG_B, RDCONTROL_ACLR_B, ADDRESS_REG_B,
OUTDATA_REG_B, OUTDATA_ACLR_B, BYTEENA_REG_B, BYTEENA_ACLR_B, INIT_FILE, INIT_FILE_LAYOUT, MAXIMUM_DEPTH, WIDTH_BYTEENA_A, WIDTH_BYTEENA_B, BYTE_SIZE,
READ_DURING_WRITE_MODE_MIXED_PORTS, RAM_BLOCK_TYPE) RETURNS (q_a[WIDTH_A - 1..0], q_b[(OPERATION_MODE == "DUAL_PORT" # OPERATION_MODE == "BIDIR_DUAL_PORT") ? WIDTH_B - 1 : 0..0] );
VHDL Component Declaration:
COMPONENT altsyncram GENERIC (
OPERATION_MODE : STRING := "SINGLE_PORT"; -- "BIDIR_DUAL_PORT";
WIDTH_A : INTEGER := 8; -- 1;
WIDTHAD_A : INTEGER := 2; -- 1;
NUMWORDS_A : INTEGER := 4; -- 1;
OUTDATA_REG_A : STRING := "UNREGISTERED";
ADDRESS_ACLR_A : STRING := "NONE";
OUTDATA_ACLR_A : STRING := "NONE";
INDATA_ACLR_A : STRING := "NONE";
WRCONTROL_ACLR_A : STRING := "NONE";
BYTEENA_ACLR_A : STRING := "NONE";
WIDTH_BYTEENA_A : INTEGER := 1;
WIDTH_B : INTEGER := 8; -- 1;
WIDTHAD_B : INTEGER := 4; -- 1;
NUMWORDS_B : INTEGER := 4; -- 1;
RDCONTROL_REG_B : STRING := "CLOCK1";
ADDRESS_REG_B : STRING := "CLOCK1";
INDATA_REG_B : STRING := "CLOCK1";
WRCONTROL_WRADDRESS_REG_B : STRING := "CLOCK1";
BYTEENA_REG_B : STRING := "CLOCK1";
OUTDATA_REG_B : STRING := "UNREGISTERED";
OUTDATA_ACLR_B : STRING := "NONE";
RDCONTROL_ACLR_B : STRING := "NONE";
INDATA_ACLR_B : STRING := "NONE";
WRCONTROL_ACLR_B : STRING := "NONE";
ADDRESS_ACLR_B : STRING := "NONE";
BYTEENA_ACLR_B : STRING := "NONE";
WIDTH_BYTEENA_B : INTEGER := 1;
BYTE_SIZE : INTEGER := 8;
READ_DURING_WRITE_MODE_MIXED_PORTS : STRING := "DONT_CARE";
RAM_BLOCK_TYPE : STRING := "AUTO";
INIT_FILE : STRING := "UNUSED";
INIT_FILE_LAYOUT : STRING := "PORT_A";
MAXIMUM_DEPTH : INTEGER := 0;
INTENDED_DEVICE_FAMILY : STRING := "STRATIX";
LPM_HINT : STRING := "BOGUS");
PORT (wren_a, wren_b, aclr0, : IN STD_LOGIC := '0';
aclr1 rden_b, clock0, clock1, : IN STD_LOGIC := '1';
clocken0, locken1 data_a : IN STD_LOGIC_VECTOR(WIDTH_A - 1 DOWNTO 0):= (OTHERS => '0');
data_b : IN STD_LOGIC_VECTOR(WIDTH_B - 1 DOWNTO 0):= (OTHERS => '0');
address_a : IN STD_LOGIC_VECTOR(WIDTHAD_A - 1 DOWNTO 0) := (OTHERS => '0');
address_b : IN STD_LOGIC_VECTOR(WIDTHAD_B - 1 DOWNTO 0) := (OTHERS => '0');
byteena_a : IN STD_LOGIC_VECTOR( (WIDTH_BYTEENA_A - 1) DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR( (WIDTH_BYTEENA_B - 1) DOWNTO 0) := (OTHERS => '1');
q_a : OUT STD_LOGIC_VECTOR(WIDTH_A - 1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR(WIDTH_B - 1 DOWNTO 0));
END COMPONENT;
VHDL LIBRARY-USE Declaration
LIBRARY altera_mf;USE altera_mf.altera_mf_components.all;
Port Descriptions:
INPUT PORTS
| Port Name | Required | Description | Comments |
|---|---|---|---|
wren_a |
No | Write enable input. | The wren_a port is not available when the OPERATION_MODE parameter is set to "ROM" mode. |
wren_b |
No | Write enable input. | The wren_b input port is available only when the OPERATION_MODE parameter is set to "BIDIR_DUAL_PORT". |
rden_b |
No | Read enable input port. | The rden_b input port is available only when the OPERATION_MODE parameter is set to "DUAL_PORT" and when the RAM_BLOCK_TYPE parameter is not set to "MEGARAM". |
data_a[] |
No | Data input port to the memory. | Input port WIDTH_A-1..0 wide. |
data_b[] |
No | Data input port to the memory. | Input port WIDTH_B-1..0 wide. |
address_a[] |
Yes | Address input to the memory. | Input port WIDTHAD_A-1..0 wide. |
address_b[] |
Yes | Address input to the memory. | Input port WIDTHAD_B-1..0 wide. |
clock0 |
Yes | Clock input port for the RAM. | |
clock1 |
No | Clock input port for the RAM. | |
clocken0 |
No | Clock enable for clock0. |
|
clocken1 |
No | Clock enable for clock1. |
|
aclr0 |
No | The first asynchronous clear input. | |
aclr1 |
No | The second asynchronous clear input. | |
byteena_a[] |
No | Byte enable input port. | Input port WIDTH_BYTEENA_A-1..0 wide. The byteena_a enable input port can be used only when the data_a port is at least two bytes wide. |
byteena_b[] |
No | Byte enable input port. | Input port WIDTH_BYTEENA_B-1..0 wide. The byteena_b enable input port can be used only when the data_b port is at least two bytes wide. |
OUTPUT PORTS
| Port Name | Required | Description | Comments |
|---|---|---|---|
q_a[] |
Yes | Data output port from the memory. | Output port WIDTH_A-1..0 wide. The q_a[] port is legal only when the OPERATION_MODE parameter is set to "SINGLE_PORT", "BIDIR_DUAL_PORT", or "ROM". |
q_b[] |
Yes | Data output port from the memory. | Output port WIDTH_B-1..0 wide. The q_b[] port is legal only when the OPERATION_MODE parameter is set to "DUAL_PORT" or "BIDIR_DUAL_PORT". |
Parameter Descriptions:
| Parameter | Type | Required | Comments |
|---|---|---|---|
OPERATION_MODE |
String | Yes | Specifies the operation of the RAM. Values are "SINGLE_PORT", "DUAL_PORT", "BIDIR_DUAL_PORT", or "ROM". If omitted, the default is "BIDIR_DUAL_PORT". |
WIDTH_A |
Integer | Yes | Specifies the width of the data_a[] input port. If omitted, the default is "1". |
WIDTHAD_A |
Integer | Yes | Specifies the width of the address_a[] input port. When the OPERATION_MODE parameter is set to "BIDIR_DUAL" mode, the WIDTH_A parameter is required. If omitted, the default is "1". |
NUMWORDS_A |
Integer | No | Number of words stored in memory. If omitted, the default is 2 ^ WIDTHAD_A. |
OUTDATA_REG_A |
String | No | Specifies the clock for the q_a[] port. Values are "CLOCK0", "CLOCK1", "UNREGISTERED", or "UNUSED". If omitted, the default is "UNREGISTERED". |
ADDRESS_ACLR_A |
String | No | Specifies the asynchronous clear for the address_a[] port. Values are "CLEAR0", "NONE", or "UNUSED". If omitted, the default is "NONE". |
OUTDATA_ACLR_A |
String | No | Specifies the asynchronous clear for the q_a[] output port. Values are "CLEAR0", "CLEAR1", "NONE", or "UNUSED". If omitted, the default is "NONE". |
INDATA_ACLR_A |
String | No | Specifies the asynchronous clear for the data_a[]input port. Values are "CLEAR0", "NONE", or "UNUSED". If omitted, the default is "NONE". |
WRCONTROL_ACLR_A |
String | No | Specifies the asynchronous clear for the wren_ainput port. Values are "CLEAR0", "NONE", or "UNUSED". If omitted, the default is "NONE". |
BYTEENA_ACLR_A |
String | No | Specifies asynchronous clear for the byteena_a input port. Values are "CLEAR0", "CLEAR1", or "NONE". If omitted, the default is "NONE". |
WIDTH_BYTEENA_A |
Integer | No | Specifies the width of the byteena_a input port. The WIDTH_BYTEENA_A parameter value must be equal to WIDTH_A / BYTE_SIZE. The WIDTH_BYTEENA_A parameter is required if the byteena_a port is specified. |
WIDTH_B |
Integer | No | Specifies the width of the data_b[] input port. When the OPERATION_MODE parameter is set to "DUAL_PORT" mode, the WIDTH_B parameter is required. If omitted, the default is "1". |
WIDTHAD_B |
Integer | No | Specifies the width of the address_b[] input port. If omitted, the default is "1". |
NUMWORDS_B |
Integer | No | Number of words stored in memory. If omitted, the default is 2 ^ WIDTHAD_B. |
RDCONTROL_REG_B |
String | No | Specifies the clock for the rden_b port during read mode. Values are "CLOCK0", "CLOCK1", or "UNUSED". If omitted, the default is "CLOCK1". |
ADDRESS_REG_B |
String | No | Specifies the clock for the address_b[] port. Values are "CLOCK0", "CLOCK1", or "UNUSED". If omitted, the default is "CLOCK1". |
INDATA_REG_B |
String | No | Specifies the clock for the data_b[] port. Values are "CLOCK0", "CLOCK1", or "UNUSED". If omitted, the default is "CLOCK1". |
WRCONTROL_WRADDRESS_REG_B |
String | No | Specifies the clock for the wren_b and address_b[] port during write mode. Values are "CLOCK0", "CLOCK1", or "UNUSED". If omitted, the default is "CLOCK1". |
BYTEENA_REG_B |
String | No | Specifies the clock for the byteena_b[] port. Values are "CLOCK0", "CLOCK1", or "UNUSED". If omitted, the default is "CLOCK1". |
OUTDATA_REG_B |
String | No | Specifies the clock for the q_b[] port. Values are "CLOCK0", "CLOCK1", "UNREGISTERED", or "UNUSED". If omitted, the default is "UNREGISTERED". |
OUTDATA_ACLR_B |
String | No | Specifies the asynchronous clear for the q_b[] output port. Values are "CLEAR0", "CLEAR1", "NONE", or "UNUSED". If omitted, the default is "NONE". |
RDCONTROL_ACLR_B |
String | No | Specifies the clear source for the port B read enable control register. Values are "CLEAR0", "CLEAR1", "NONE", or "UNUSED". The default value is "NONE". |
INDATA_ACLR_B |
String | No | Specifies the asynchronous clear for the data_b[]input port. Values are "CLEAR0", "NONE", or "UNUSED". If omitted, the default is "NONE". |
WRCONTROL_ACLR_B |
String | No | Specifies the asynchronous clear for the wren_binput port. Values are "CLEAR0", "NONE", or "UNUSED". If omitted, the default is "NONE". |
ADDRESS_ACLR_B |
String | No | Specifies the asynchronous clear for the address_b[] port. Values are "CLEAR0", "NONE", or "UNUSED". If omitted, the default is "NONE". |
BYTEENA_ACLR_B |
String | No | Specifies asynchronous clear for the byteena_b input port. Values are "CLEAR0", "CLEAR1", "NONE", or "UNUSED". If omitted, the default is "NONE". |
WIDTH_BYTEENA_B |
Integer | No | Specifies the width of the byteena_b input port. The WIDTH_BYTEENA_B parameter value must be equal to WIDTH_B / BYTE_SIZE. The WIDTH_BYTEENA_B parameter is required if the byteena_b port is specified. |
BYTE_SIZE |
Integer | No | Specifies the byte enable size. Values are "8" or "9". If omitted, the default is "8". |
READ_DURING_WRITE_MODE_MIXED_PORTS |
String | No | Specifies the behavior when the read and write operations occur at different ports on the same RAM address. Values are "OLD_DATA" or "DONT_CARE". The default value is "DONT_CARE". When the OPERATION_MODE parameter is set to "MEGARAM", the READ_DURING_WRITE_MODE_MIXED_PORTS parameter must be set to "DONT_CARE". |
RAM_BLOCK_TYPE |
String | No | Specifies the RAM block type. Values are "M512", "M4K", "MEGARAM", or "AUTO". If omitted, the default is "AUTO". |
INIT_FILE |
String | No | Name of the Memory Initialization File (.mif) or Hexadecimal (Intel-Format) Output File (.hexout) containing RAM initialization data ("<file name>"), or "UNUSED". The default is "UNUSED". The INIT_FILE parameter is unavailable when the RAM_BLOCK_TYPE parameter is set to MEGARAM. When the OPERATION_MODE parameter is set to "DUAL_PORT", the Compiler uses only the WIDTH_B parameters to read the initialization file. |
INIT_FILE_LAYOUT |
String | No | Specifies the layout port used with the initialization file. Values are "PORT_A" or "PORT_B". If the OPERATION_MODE is set to "DUAL_PORT" mode, the default value is "PORT_B". If the OPERATION_MODE is set to other modes, the the default value is "PORT_A". |
MAXIMUM_DEPTH |
Integer | No | Specifies the maximum segmented value of the RAM. The MAXIMUM_DEPTH parameter value depends on the RAM_BLOCK_TYPE parameter. If omitted, the default is "0". |
INTENDED_DEVICE_FAMILY |
String | No | This parameter is used for modeling and behavioral simulation purposes. Create the PLL with the MegaWizard Plug-in Manager to calculate the value for this parameter. |
LPM_HINT |
String | No | Allows you to assign Altera-specific parameters in VHDL Design Files (.vhd). If omitted, the default is "UNUSED". |
