AXI Ordering
最近重新整理了一下AXI协议里对于ordering的描述，总结在下面，这里其实有很多实现相关的方式，协议里只是给了一些指导意见，对于具体的做法就需要实战中再看具体情况了，比如ID位宽在哪个节点扩展，系统如果有PCIe的ordering，如何高效的保序，减少性能影响；如果涉及到非一致性域到一致性域的转换，如何在不同协议之间保序，这些都是实际中遇到过的问题，后面有时间再继续总结。
Definition of the ordering model:
AXI4 protocol supports an ordering model based on the use of the AXI ID transaction identifier
The principles are that for transactions with the same ID:
- Transactions to any single peripheral device, must arrive at the peripheral in the ordering in which they are issued, regardless of the addresses of the transactions.
- 发向单个device的，必须按顺序，不管地址
- Memory transactions that use the same, or overlapping, addresses must arrive at the memory in the order in which they are issued.
- 访存传输，如果地址hazard, 必须按顺序
Note:
In an AXI system with multiple masters, the AXI IDs used for the ordering model include the infrastructure IDs, that identify each master uniquely. This means the ordering model applies independently to each master in the system.
每个master单独执行ordering rules.
The AXI ordering model also requires that all transactions with the same ID in the same direction must provide their responses in the order in which they are issued.
同一个ID同方向的传输，response也要in order
Because the read and write address channels are independent, if an ordering ordering relationship is required between two transactions with the same ID that are in different directions, then a master must wait to receive a response to the first transactions before issuing the second transaction.
不同方向的顺序要等待，显而易见，不需要多说
而且即使收到了response, 这个response如果是中间节点给的，也无法保证顺序。
Master Ordering
A master that issues multiple transactions in the same direction, read or write, with the same ID has the following guarantees about the ordering of these transactions.
- The order of response at the master to all transactions must be the same as the order of issue.
- Master收到的response要保序
- For transactions to Device memory, the order of arrival at the slave must be the same as the order of issue.
- 发送到device的，到达的顺序要保持.
- For normal memory, the order of arrival at the slave of transactions to the same or overlapping addresses, must be the same as the order of issue. This applies also, to transactions to cacheable memory. That is , it applies to all valid transactions for which AxCACHE[3:1] is not 0b000.
- 对于normal memory, 如果地址hazard, 则到达slave要保序。
Interconnect ordering:
To meet the requirements of the ordering model, the interconnect must ensure that:
- The order of transactions in the same direction with the same ID to Device memory is preserved.
- 同方向，同ID，发送到Device的传输要保序
- The order of transactions in the same direction with the same ID to the same or overlapping addresses is preserved.
- 同方向，同ID，地址hazard，要保序
- The order of write responses with the same ID is preserved.
- 同ID的write response要保序
- The order of read responses with the same ID is preserved.
- 同ID的read response要保序
- Any manipulation of the AXI ID values associated with a transaction must ensure that the ordering requirements of the original ID values are maintained.
- 对ID的操作，要保证原始ID的顺序要求可以满足
- Any component that gives a response to a transaction before the transaction reaches its final destination must ensure that the ordering requirements given in this section are maintained until the transaction reaches its final destination.
- 对于Posted write, 中间节点要负责完整保序
Slave Ordering
To meet the requirements of the ordering model, a slave must ensure that:
- Any write transaction for which it has issued a response must be observed by any subsequent write or read transaction, regardless of the transaction IDs.
- 对于slave发出的write response, 要保证对后面的读写可见，无论ID
- Any write transaction to Device memory must be observed by any subsequent write to Device memory with the same ID, even if a response has not yet been issued.
- 即使没发response，对Device 的同ID写也要被后面的写可见
- 还没给response，怎么保证能被看到？
- Any write transaction to Normal memory must be observed by any subsequent write to the same or an overlapping address with the same ID, even if a response has not yet been given.
- 对同ID地址hazard的normal memory写，即使没有给response，也要能被后面的传输看到
- Responses to multiple write transactions with different IDs can be issued in any order.
- 不同ID的response可以乱序
- Any read transaction for which it has issued a response must be observed by any subsequent write or read transaction, regardless of the transaction IDs.
- 不论ID，读要被后面的操作看到.
- Any read transaction to Device memory must be observed by any subsequent read to Device memory with the same ID, even if a response has not yet been issued.
- 同ID对Device'的访问，必须被后面的操作看到。
- Responses to multiple read transactions with the same ID must be issued in the order in which the transactions arrive.
- 对于同ID的读，response要按顺序发
- Responses to multiple read transactions with different IDs can be issued in any order.
- 不同ID的读，response可以乱序
- 如果这样，read->write->read, 对同一地址的操作，两次读数据不同，是否需要保序？
- 如果要保证读到最新的数据，要么等前一笔write结束，要么是同一个ID。
Response before final destination:
Any intermediate component that issues a transaction response before the transaction has reached its final destination , must ensure visibility of the transaction to any transactions from any upstream masters.
- Posted write, 中间节点要负责保证数据consistency.
The requirements are:
- For accesses to all memory types, any subsequent transaction to the same or an overlapping address must observe the transaction for which the intermediate component issues a response.
- Memory访问，地址和hazard的后一笔，要能看到前一笔的post write response.
- 如何保证？其实就是保序
- For accesses to Device memory, the intermediate component must also maintain the ordering of any subsequent transaction with the same ID and to the same slave, relative to the transaction for which it issued a response.
- Device访问，中间节点要对同ID和同slave目标的传输保序
An intermediate response can only be given to a transaction when the AxCACHE attribute indicates that it is permissible to do so.
要看AxCache
Transaction marked as Normal can be converted to Device without removing any of its original guarantees. To meet this requirement, the behavior for Device memory accesses to the same or overlapping addresses must be the same as for Normal memory accesses, regardless of the ID values.
对地址hazard，device传输也不看ID，要保序
Ordered write observation
To improve compatibility with interface protocols that support a different ordering model an Ordered_Write_Observation property is defined that can be True or False for a single interface.
An interface that supports the Ordered_Write_Observation property can support the Producer/Consumer ordering model with improved performance.
这部分没有实现上的指导作用
Ordered_Write_Observation property
