04 2018 档案

摘要:Verilog/VHDL Synthesis (even just for FPGA) Static Timing (setup time/hold time) Back-annotated gate level simulation Basic digital design concepts (F 阅读全文
posted @ 2018-04-05 12:35 TheNotesOfEli 阅读(161) 评论(0) 推荐(0) 编辑