A Verilog HDL Primer___第二章代码

module fa_str(a,b,cin,sum,cout);
    input a,b,cin;
    output sum,cout;
    wire s1,t1,t2,t3;
    xor 
        ux1(s1,a,b),
        ux2(sum,s1,cin);
    and 
        ua1(t3,a,b),
        ua2(t2,b,cin),
        ua3(t1,a,cin);
    or
        uo1(cout,t1,t2,t3);
endmodule

//`include "fa_str.v"
module four_bit_fa(fa,fb,fcin,fsum,fcout);
    parameter SIZE = 4;
    input[SIZE: 1] fa,fb;
    output[SIZE: 1] fsum;
    input fcin;
    input fcout;
    wire[SIZE-1:1] ftemp;

    fa_str
        ufa1 (// 按照对应端口名连接
            .a(fa[1]), .b(fb[1]), .cin(fcin),
            .sum(fsum[1]), .cout(ftemp[1])
        ),
        ufa2 (// 按照对应端口名连接
            .a(fa[2]), .b(fb[2]), .cin(ftemp[1]),
            .sum(fsum[2]), .cout(ftemp[2])
        ),
        ufa3 (// 按照端口顺序连接
            fa[3],fb[3],ftemp[2],fsum[3],ftemp[3]
        ),
        ufa4 (// 按照端口顺序连接
            fa[4],fb[4],ftemp[3],fsum[4],fcout
        );
endmodule

 

module fa_mix(
        input a,b,cin,
        output sum,
        output reg cout
        );
    reg t1,t2,t3;
    wire s1;
    xor ux1(s1,a,b);   // 门实例语句
    
    always
        @( a or b or cin  ) begin   // always语句
            t1 = a&cin;             // 阻塞赋值
            t2 = b&cin;             
            t3 = a&b;
            cout <= (t1|t2)|t3;     // 非阻塞赋值
        end
    assign sum = s1^cin;            // 连续赋值语句
endmodule

 fa_seq.v

module fa_seq(a,b,cin,sum,cout);
input a,b,cin;
output reg sum,cout;
reg t1,t2,t3;

always
    @( a or b or cin ) begin
        sum <= (a-b)-cin;
        t1 = a&cin;
        t2 = b&cin;
        t3 = a&b;
        cout <= (t1|t2)|t3;
    end
endmodule

fa_seq.vt

`timescale 1ns/1ns
module fa_top;
    reg pa,pb,pci;
    wire pco,psum;
    
    // 实例引用被测模块：
    fa_seq uf1(
        pa,pb,pci,psum,pco
        );
    
    initial
        begin:  blk_only_once
            reg [3:0] pal;
                //需要4位， pal才能取值8
                for( pal = 0; pal < 8; pal=pal+1)
                    begin
                        {pa,pb,pci}<= pal;
                        #5 $display("pa,pb,pci = %b %b %b",pa,pb,pci,
                                " : : : pco,psum = %b%b",pco,psum);
                end
        end
endmodule