摘要: 1、并转串 代码: module parallel_serial( clk, rst_n, en, data_i, data_o ); input clk, rst_n,en; input [7:0] data_i; output data_o; reg [7:0] data_buf; always 阅读全文
posted @ 2020-12-16 19:32 LiYiRui 阅读(613) 评论(0) 推荐(0) 编辑