Verilog 同步FIFO 实现方式2

`timescale 1ns / 1ps
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// Company:
// Engineer:
//
// Create Date:    15:40:04 01/06/2010
// Design Name:
// Module Name:    fifo_syn1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo_syn1(
datain,
rd,
wr,
rst,
clk,
dataout,
full,
empty
    );

input [15:0] datain;
input rd, wr, rst, clk;
output [15:0] dataout;
output full, empty;

reg [15:0] dataout;
reg full_in, empty_in;
reg [15:0] mem [4095:0];
reg [11:0] rp, wp;

assign full = full_in;
assign empty = empty_in;  
 
// memory read out  
always@(posedge clk) begin
  if(rd && ~empty_in) dataout = mem[rp];
  end

// memory write in
always@(posedge clk) begin
    if(wr && ~full_in) mem[wp]<=datain;
  end   
 
 
  // memory write pointer increment
 always@(posedge clk or negedge rst)
    if(!rst)
        wp<=0;
    else   wp <= (wr && ~full_in) ? (wp + 1'b1) : wp;
    

// memory read pointer increment
  always@(posedge clk or negedge rst)
    if(!rst)
       rp <= 0;
    else  rp <= (rd && ~empty_in)? (rp + 1'b1): rp;
    
    
// Full signal generate
  always@(posedge clk or negedge rst) begin
    if(!rst) full_in <= 1'b0;
    else begin
      if( (~rd && wr)&&((wp==rp-1)||(rp==4'h0&&wp==4'hf)))
          full_in <= 1'b1;
      else if(full_in && rd) full_in <= 1'b0;
    end
  end   
 

  // Empty signal generate
  always@(posedge clk or negedge rst) begin
    if(!rst) empty_in <= 1'b1;
    else begin
      if((rd&&~wr)&&(rp==wp-1 || (rp==4'hf&&wp==4'h0)))
        empty_in<=1'b1;
      else if(empty_in && wr) empty_in<=1'b0;
    end
  end
 
    
endmodule