当Linux驱动读出寄存器数据与写入寄存器数据不一样时，检查FPGA时序

FPGA设计：

   //写pwm频率寄存器 & 占空比寄存器
always@(posedge clk or negedge reset_n)
    if(!reset_n) begin
        cnt_freq <= 32'd0;
        cnt_duty <= 32'd0;
    end
    else if(as_write)begin
            if(as_address==0) cnt_freq <= as_writedata;
        else cnt_duty <= cnt_duty;
            if(as_address==1) cnt_duty <= as_writedata;
        else cnt_freq <= cnt_freq;
    end

 

 

结果：

 

修改设计：

//写pwm频率寄存器
always@(posedge clk or negedge reset_n)
    if(!reset_n) begin
        cnt_freq <= 32'd0;
    end
    else if(as_write && (as_address == 0))begin
        cnt_freq <= as_writedata;
    end
    else begin
        cnt_freq <= cnt_freq;
    end
//写pwm占空比寄存器
always@(posedge clk or negedge reset_n)
    if(!reset_n) begin
        cnt_duty <= 32'd0;
    end
    else if(as_write && (as_address == 1)) begin
        cnt_duty <= as_writedata;
    end
    else begin
        cnt_duty <= cnt_duty;
    end

 

 

结果：