ZedBoard学习笔记（二）AXI总线

主要借鉴超群天晴的两篇博客，链接如下：

http://www.cnblogs.com/surpassal/archive/2012/10/07/Zedboard_Lab3.html

http://www.cnblogs.com/surpassal/archive/2012/10/09/Zynq_Lab4.html

我的开发环境：

硬件：Diligent Zedboard

OS：Windows XP 32bit

软件：PlanAhead 14.4 + XPS 14.4 + SDK 14.4

只记录下我遇到的问题：

1. 在第一个实验Generate Bitstream时遇到错误：

ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned. 
This may cause I/O contention or incompatibility with the board power or
connectivity affecting performance, signal integrity or in extreme cases
cause damage to the device or the components to which it is connected. To
prevent this error, it is highly suggested to specify all pin locations and
I/O standards to avoid potential contention or conflicts and allow proper
bitstream creation. To demote this error to a warning and allow bitstream
creation with unspecified I/O location or standards, you may apply the
following bitgen switch: -g UnconstrainedPins:Allow

解决方法：把LD连在GPIO_IO而不是GPIO_IO_O上，如下图所示：

2. 在SDK中Program FPGA时遇到如下错误：Program FPGA failed：FPGA configuration encountered errors.

解决方法：　首先检查是否连JTAG线，板子开关是否打开。

　　　　　　其次检查在XPS中是否Import了正确的xml配置文件，我就是因为在XPS中忘记导入xml文件才产生的这个错误。　　　　　　　导入后记得重新launch SDK。

3. 修改main函数时发现超群天晴的main函数中的print函数编译有错，最后注释掉函数声明void print(char * ptr)后，将main函数中的print改为printf即可编译通过，并且成功运行。