简单的nios II 流水灯 硬件部分

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简单的nios II 流水灯

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硬件平台：康草EP2C5-V5

  　　　　 FPGA :EP2C5Q208C8N

              SDRAM:K4S641632k

              Flash:JS28F640

              4位led

软件平台：Microsoft Windows xp Professional sp3(深度D版)

              Quartus II 10.0 SP1 Build: 262 

              Nios II IDE 10.0 SP1 Build: 262

一、硬件
1.新建Quartus 工程

Next>   Next>

Finish

2.构建sopc

2.1调出SOPC Builder

2.2建立系统

2.2.1配置系统时钟

2.3查找并添加Nios II processor

cup配置

弄个高速的cup玩玩，按个人喜好配置。

 Next>

 如此配置原因是AVIC(马瑞)博客中提到“NIOS II下关于无法进行寄存器操作PIO的问题解析”

Next>

JTAG Debug Module 选择 Leve 1

Finish

2.4添加SDRAM Controller

康草EP2c5-v5上SDRAM是SAMSUNG K4S641632K

其Memory Profile配置如下

Timing时序配置

2.5 添加Flash

由于altra采用具有avalon接口的CFI控制器与Flash相连，所以添加Flash Memory (Common Flash Interface)

康草EP2c5-v5上Flash是JS28F640 其地址位宽23，数据位宽8位，Attributes 配置如下

Next>

其Triming配置

Finish

然后系统提示

Error: cfi_flash_0: cfi_flash_0.s1 must be connected to an Avalon-MM Tristate master

这是因为CFI控制器需要Avalon-MM Tristate master

2.5添加Avalon-MM Tristate Brideg

默认选择

Finish

由于CFI需要Avalon-MM Tristate master，看到图中的小叉叉没，表示没有连接，我们要将他们连接起来

当鼠标靠近那个小叉叉时时，tristate master会自动连向我们刚才添加的CFI，并且连接点是一个小白点，表示连接可以，鼠标拿开时他们又断开了

这时我们只需点击那个小白点，他们就连接起来了。

连接好了，是不是很有趣。

2.添加 JTAG UART

JTAG UART可以用于观察调试数据，调试时可设置将数据发送到Nios IDE调试界面，便于程序调试

默认配置

Finish

2.添加PIO

PIO用于输入输出

 

配置为only output，康草EP2C5-V5板上只有4个led

Finish

添加system ID

此组件不用配置

Finish

至此，添加组建基本完成，还需设置

将组件名字改成自己需要的名字

但组件名不能和工程名相同，不然Quartus编译时会出现"Project too complex: hierarchy path is too long”的错误

我改成了如下图

现在设置CPU 的 reset vector 和 Exception Vector

双击CPU，点击 reset vector   Memory 下拉窗 选择 cfi_flash

点击 Exception Vector memory 下拉窗 选择 sdram

Finish

然后锁定flash地址，将flash存储器地址锁定为0，cup复位后从flash内代码开始执行

点击cfi_flash Base 栏中的小锁标志

点击后，该小锁变黑，表示锁定了。

然后自动分配地址，中断号

点击system 下 Auto-Assign Base Addresses

再点击system 下 Auto-Assign Base IRQs

检查无错误，无警告。

至此，sopc配置已经完成

点击Next，配置是否产生仿真文件

点击Generate

Save

系统开始编译了，编译较慢，需等较长的时间，可以远眺一下，放松一下眼睛，感谢Altera为广大电子工程师考虑，提醒大家长时间盯电脑后，需要让眼睛休息一下，这就是休息时间。呵呵

提示Info: System generation was successful.

成功

现在Exit，回到Quartus II

New 一个 Block Diagram/Schematic File

双击空白处，添加刚才用sopc buider 建立的 system_led

再添加 altpll 锁相环

 板上时钟50Mhz

Next

取消全部

Next

Next

clk0设置

Next

clk1设置

clk1用于驱动SDRAM，需要-75dge的相差

Finish

将altpll与system_led相连，并generation pins，将inclk0改为clk，c1改为zs_clk_from_the_sdram

注意generation pins时，有些引脚名会在末尾产生多余的一个空格，如果引脚配置不成功的话，需要检查一下generation 的pin name是不是多了一个空格

保存为led.bdf加入工程

新建tcl脚本文件，配置引脚

以下为本工程EP2C5-V5引脚配置脚本

#Setup.tcl
# Setup pin setting for EP2C5 main board 
# nios led
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF

set_location_assignment PIN_23 -to clk
set_location_assignment PIN_56 -to reset_n
#led
set_location_assignment PIN_6 -to out_port_from_the_led_pio\[0\]
set_location_assignment PIN_5 -to out_port_from_the_led_pio\[1\]
set_location_assignment PIN_3 -to out_port_from_the_led_pio\[2\]
set_location_assignment PIN_4 -to out_port_from_the_led_pio\[3\]
#flash
set_location_assignment PIN_201 -to select_n_to_the_cfi_flash
set_location_assignment PIN_168 -to read_n_to_the_cfi_flash
set_location_assignment PIN_165 -to write_n_to_the_cfi_flash

set_location_assignment PIN_181 -to address_to_the_cfi_flash\[0\]
set_location_assignment PIN_193 -to address_to_the_cfi_flash\[1\]
set_location_assignment PIN_192 -to address_to_the_cfi_flash\[2\]
set_location_assignment PIN_191 -to address_to_the_cfi_flash\[3\]
set_location_assignment PIN_189 -to address_to_the_cfi_flash\[4\]
set_location_assignment PIN_188 -to address_to_the_cfi_flash\[5\]
set_location_assignment PIN_187 -to address_to_the_cfi_flash\[6\]
set_location_assignment PIN_185 -to address_to_the_cfi_flash\[7\]
set_location_assignment PIN_197 -to address_to_the_cfi_flash\[8\]
set_location_assignment PIN_195 -to address_to_the_cfi_flash\[9\]
set_location_assignment PIN_199 -to address_to_the_cfi_flash\[10\]
set_location_assignment PIN_198 -to address_to_the_cfi_flash\[11\]
set_location_assignment PIN_200 -to address_to_the_cfi_flash\[12\]
set_location_assignment PIN_205 -to address_to_the_cfi_flash\[13\]
set_location_assignment PIN_203 -to address_to_the_cfi_flash\[14\]
set_location_assignment PIN_207 -to address_to_the_cfi_flash\[15\]
set_location_assignment PIN_206 -to address_to_the_cfi_flash\[16\]
set_location_assignment PIN_208 -to address_to_the_cfi_flash\[17\]
set_location_assignment PIN_14 -to address_to_the_cfi_flash\[18\]
set_location_assignment PIN_13 -to address_to_the_cfi_flash\[19\]
set_location_assignment PIN_12 -to address_to_the_cfi_flash\[20\]
set_location_assignment PIN_11 -to address_to_the_cfi_flash\[21\]
set_location_assignment PIN_10 -to address_to_the_cfi_flash\[22\]

set_location_assignment PIN_180 -to data_to_and_from_the_cfi_flash\[0\]
set_location_assignment PIN_179 -to data_to_and_from_the_cfi_flash\[1\]
set_location_assignment PIN_176 -to data_to_and_from_the_cfi_flash\[2\]
set_location_assignment PIN_175 -to data_to_and_from_the_cfi_flash\[3\]
set_location_assignment PIN_173 -to data_to_and_from_the_cfi_flash\[4\]
set_location_assignment PIN_171 -to data_to_and_from_the_cfi_flash\[5\]
set_location_assignment PIN_170 -to data_to_and_from_the_cfi_flash\[6\]
set_location_assignment PIN_169 -to data_to_and_from_the_cfi_flash\[7\]

#SDRAM
set_location_assignment PIN_31 -to zs_dq_to_and_from_the_sdram\[0\]
set_location_assignment PIN_30 -to zs_dq_to_and_from_the_sdram\[1\]
set_location_assignment PIN_33 -to zs_dq_to_and_from_the_sdram\[2\]
set_location_assignment PIN_35 -to zs_dq_to_and_from_the_sdram\[3\]
set_location_assignment PIN_34 -to zs_dq_to_and_from_the_sdram\[4\]
set_location_assignment PIN_37 -to zs_dq_to_and_from_the_sdram\[5\]
set_location_assignment PIN_39 -to zs_dq_to_and_from_the_sdram\[6\]
set_location_assignment PIN_41 -to zs_dq_to_and_from_the_sdram\[7\]
set_location_assignment PIN_77 -to zs_dq_to_and_from_the_sdram\[8\]
set_location_assignment PIN_60 -to zs_dq_to_and_from_the_sdram\[9\]
set_location_assignment PIN_59 -to zs_dq_to_and_from_the_sdram\[10\]
set_location_assignment PIN_58 -to zs_dq_to_and_from_the_sdram\[11\]
set_location_assignment PIN_57 -to zs_dq_to_and_from_the_sdram\[12\]
set_location_assignment PIN_45 -to zs_dq_to_and_from_the_sdram\[13\]
set_location_assignment PIN_48 -to zs_dq_to_and_from_the_sdram\[14\]
set_location_assignment PIN_47 -to zs_dq_to_and_from_the_sdram\[15\]

set_location_assignment PIN_82 -to zs_addr_from_the_sdram\[0\]
set_location_assignment PIN_86 -to zs_addr_from_the_sdram\[1\]
set_location_assignment PIN_88 -to zs_addr_from_the_sdram\[2\]
set_location_assignment PIN_87 -to zs_addr_from_the_sdram\[3\]
set_location_assignment PIN_70 -to zs_addr_from_the_sdram\[4\]
set_location_assignment PIN_69 -to zs_addr_from_the_sdram\[5\]
set_location_assignment PIN_68 -to zs_addr_from_the_sdram\[6\]
set_location_assignment PIN_67 -to zs_addr_from_the_sdram\[7\]
set_location_assignment PIN_72 -to zs_addr_from_the_sdram\[8\]
set_location_assignment PIN_75 -to zs_addr_from_the_sdram\[9\]
set_location_assignment PIN_84 -to zs_addr_from_the_sdram\[10\]
set_location_assignment PIN_74 -to zs_addr_from_the_sdram\[11\]

set_location_assignment PIN_81 -to zs_ba_from_the_sdram\[0\]
set_location_assignment PIN_80 -to zs_ba_from_the_sdram\[1\]

set_location_assignment PIN_40 -to zs_dqm_from_the_sdram\[0\]
set_location_assignment PIN_61 -to zs_dqm_from_the_sdram\[1\]

set_location_assignment PIN_76 -to zs_cs_n_from_the_sdram
set_location_assignment PIN_46 -to zs_ras_n_from_the_sdram
set_location_assignment PIN_43 -to zs_cas_n_from_the_sdram
set_location_assignment PIN_44 -to zs_we_n_from_the_sdram
set_location_assignment PIN_63 -to zs_cke_from_the_sdram
set_location_assignment PIN_64 -to zs_clk_from_the_sdram

保存后，将led.bdf set as top-Leve Entity

然后run刚才的.tcl脚本文件

引脚配置成功

最后Start Compilation

成功，下载到fpga实验板，硬件部分就完成了。