AXI-IP-vivado-&-跨时钟
Register ready signals in low latency, zero bubble pipeline
https://www.itdev.co.uk/blog/pipelining-axi-buses-registered-ready-signals
Crossing in four parts
https://www.fpga4fun.com/CrossClockDomain.html
面向axi总线的uart ip核设计
https://www.doc88.com/p-0834877403277.html
跨时钟域传递数据实例分析
https://www.cnblogs.com/east1203/p/11521568.html
附录的论文粘过来
附录
1. Synthesis and Scripting Techniques for Designing MultiAsynchronous Clock Designs
2. Simulation and Synthesis Techniques for Asynchronous FIFO Design
3. Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
------------------------------------------------------------------------------
up_axi 一个将axi_lite接口转换成寄存器接口的模块
https://blog.csdn.net/mcupro/article/details/99830580
AXI4-Lite接口转普通ram接口
不过这个没有跨时钟域
https://blog.csdn.net/Real003/article/details/88938040
Crossing clock domains with AXI Interconnect. Doing it right
