摘要：
moduledetect_module(CLK,RSTn,RX_Pin_In,H2L_Sig);inputCLK;inputRSTn;inputRX_Pin_In;outputH2L_Sig;regH2L_F1;regH2L_F2;always@(posedgeCLKornegedgeRSTn)if(!RSTn)//有无复位beginH2L_F1<=1'b1;H2L_F2<=1'b1;//非阻塞语句endelsebeginH2L_F1<=RX_Pin_In;H2L_F2<=H2L_F1;endassignH2L_Sig=H2L_F2&!H2L_F 阅读全文
